xtensa: add s32c1i-based atomic ops implementations
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
This commit is contained in:
Max Filippov
Chris Zankel
parent
00273125c3
commit
219b1e4c61
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@ -66,19 +66,35 @@
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*/
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static inline void atomic_add(int i, atomic_t * v)
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{
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unsigned int vval;
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#if XCHAL_HAVE_S32C1I
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unsigned long tmp;
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int result;
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__asm__ __volatile__(
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"rsil a15, "__stringify(LOCKLEVEL)"\n\t"
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"l32i %0, %2, 0 \n\t"
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"add %0, %0, %1 \n\t"
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"s32i %0, %2, 0 \n\t"
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"wsr a15, ps \n\t"
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"rsync \n"
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: "=&a" (vval)
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: "a" (i), "a" (v)
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: "a15", "memory"
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);
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__asm__ __volatile__(
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"1: l32i %1, %3, 0\n"
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" wsr %1, scompare1\n"
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" add %0, %1, %2\n"
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" s32c1i %0, %3, 0\n"
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" bne %0, %1, 1b\n"
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: "=&a" (result), "=&a" (tmp)
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: "a" (i), "a" (v)
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: "memory"
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);
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#else
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unsigned int vval;
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__asm__ __volatile__(
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" rsil a15, "__stringify(LOCKLEVEL)"\n"
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" l32i %0, %2, 0\n"
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" add %0, %0, %1\n"
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" s32i %0, %2, 0\n"
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" wsr a15, ps\n"
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" rsync\n"
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: "=&a" (vval)
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: "a" (i), "a" (v)
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: "a15", "memory"
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);
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#endif
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}
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/**
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@ -90,19 +106,35 @@ static inline void atomic_add(int i, atomic_t * v)
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*/
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static inline void atomic_sub(int i, atomic_t *v)
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{
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unsigned int vval;
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#if XCHAL_HAVE_S32C1I
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unsigned long tmp;
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int result;
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__asm__ __volatile__(
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"rsil a15, "__stringify(LOCKLEVEL)"\n\t"
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"l32i %0, %2, 0 \n\t"
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"sub %0, %0, %1 \n\t"
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"s32i %0, %2, 0 \n\t"
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"wsr a15, ps \n\t"
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"rsync \n"
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: "=&a" (vval)
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: "a" (i), "a" (v)
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: "a15", "memory"
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);
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__asm__ __volatile__(
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"1: l32i %1, %3, 0\n"
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" wsr %1, scompare1\n"
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" sub %0, %1, %2\n"
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" s32c1i %0, %3, 0\n"
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" bne %0, %1, 1b\n"
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: "=&a" (result), "=&a" (tmp)
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: "a" (i), "a" (v)
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: "memory"
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);
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#else
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unsigned int vval;
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__asm__ __volatile__(
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" rsil a15, "__stringify(LOCKLEVEL)"\n"
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" l32i %0, %2, 0\n"
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" sub %0, %0, %1\n"
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" s32i %0, %2, 0\n"
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" wsr a15, ps\n"
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" rsync\n"
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: "=&a" (vval)
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: "a" (i), "a" (v)
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: "a15", "memory"
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);
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#endif
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}
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/*
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@ -111,40 +143,78 @@ static inline void atomic_sub(int i, atomic_t *v)
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static inline int atomic_add_return(int i, atomic_t * v)
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{
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unsigned int vval;
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#if XCHAL_HAVE_S32C1I
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unsigned long tmp;
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int result;
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__asm__ __volatile__(
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"rsil a15,"__stringify(LOCKLEVEL)"\n\t"
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"l32i %0, %2, 0 \n\t"
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"add %0, %0, %1 \n\t"
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"s32i %0, %2, 0 \n\t"
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"wsr a15, ps \n\t"
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"rsync \n"
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: "=&a" (vval)
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: "a" (i), "a" (v)
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: "a15", "memory"
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);
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__asm__ __volatile__(
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"1: l32i %1, %3, 0\n"
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" wsr %1, scompare1\n"
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" add %0, %1, %2\n"
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" s32c1i %0, %3, 0\n"
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" bne %0, %1, 1b\n"
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" add %0, %0, %2\n"
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: "=&a" (result), "=&a" (tmp)
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: "a" (i), "a" (v)
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: "memory"
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);
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return vval;
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return result;
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#else
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unsigned int vval;
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__asm__ __volatile__(
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" rsil a15,"__stringify(LOCKLEVEL)"\n"
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" l32i %0, %2, 0\n"
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" add %0, %0, %1\n"
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" s32i %0, %2, 0\n"
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" wsr a15, ps\n"
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" rsync\n"
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: "=&a" (vval)
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: "a" (i), "a" (v)
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: "a15", "memory"
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);
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return vval;
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#endif
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}
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static inline int atomic_sub_return(int i, atomic_t * v)
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{
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unsigned int vval;
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#if XCHAL_HAVE_S32C1I
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unsigned long tmp;
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int result;
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__asm__ __volatile__(
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"rsil a15,"__stringify(LOCKLEVEL)"\n\t"
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"l32i %0, %2, 0 \n\t"
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"sub %0, %0, %1 \n\t"
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"s32i %0, %2, 0 \n\t"
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"wsr a15, ps \n\t"
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"rsync \n"
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: "=&a" (vval)
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: "a" (i), "a" (v)
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: "a15", "memory"
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);
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__asm__ __volatile__(
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"1: l32i %1, %3, 0\n"
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" wsr %1, scompare1\n"
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" sub %0, %1, %2\n"
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" s32c1i %0, %3, 0\n"
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" bne %0, %1, 1b\n"
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" sub %0, %0, %2\n"
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: "=&a" (result), "=&a" (tmp)
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: "a" (i), "a" (v)
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: "memory"
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);
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return vval;
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return result;
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#else
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unsigned int vval;
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__asm__ __volatile__(
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" rsil a15,"__stringify(LOCKLEVEL)"\n"
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" l32i %0, %2, 0\n"
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" sub %0, %0, %1\n"
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" s32i %0, %2, 0\n"
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" wsr a15, ps\n"
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" rsync\n"
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: "=&a" (vval)
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: "a" (i), "a" (v)
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: "a15", "memory"
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);
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return vval;
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#endif
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}
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/**
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@ -251,38 +321,70 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
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static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
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{
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unsigned int all_f = -1;
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unsigned int vval;
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#if XCHAL_HAVE_S32C1I
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unsigned long tmp;
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int result;
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__asm__ __volatile__(
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"rsil a15,"__stringify(LOCKLEVEL)"\n\t"
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"l32i %0, %2, 0 \n\t"
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"xor %1, %4, %3 \n\t"
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"and %0, %0, %4 \n\t"
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"s32i %0, %2, 0 \n\t"
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"wsr a15, ps \n\t"
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"rsync \n"
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: "=&a" (vval), "=a" (mask)
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: "a" (v), "a" (all_f), "1" (mask)
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: "a15", "memory"
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);
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__asm__ __volatile__(
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"1: l32i %1, %3, 0\n"
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" wsr %1, scompare1\n"
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" and %0, %1, %2\n"
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" s32c1i %0, %3, 0\n"
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" bne %0, %1, 1b\n"
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: "=&a" (result), "=&a" (tmp)
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: "a" (~mask), "a" (v)
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: "memory"
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);
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#else
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unsigned int all_f = -1;
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unsigned int vval;
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__asm__ __volatile__(
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" rsil a15,"__stringify(LOCKLEVEL)"\n"
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" l32i %0, %2, 0\n"
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" xor %1, %4, %3\n"
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" and %0, %0, %4\n"
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" s32i %0, %2, 0\n"
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" wsr a15, ps\n"
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" rsync\n"
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: "=&a" (vval), "=a" (mask)
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: "a" (v), "a" (all_f), "1" (mask)
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: "a15", "memory"
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);
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#endif
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}
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static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
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{
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unsigned int vval;
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#if XCHAL_HAVE_S32C1I
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unsigned long tmp;
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int result;
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__asm__ __volatile__(
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"rsil a15,"__stringify(LOCKLEVEL)"\n\t"
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"l32i %0, %2, 0 \n\t"
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"or %0, %0, %1 \n\t"
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"s32i %0, %2, 0 \n\t"
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"wsr a15, ps \n\t"
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"rsync \n"
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: "=&a" (vval)
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: "a" (mask), "a" (v)
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: "a15", "memory"
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);
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__asm__ __volatile__(
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"1: l32i %1, %3, 0\n"
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" wsr %1, scompare1\n"
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" or %0, %1, %2\n"
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" s32c1i %0, %3, 0\n"
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" bne %0, %1, 1b\n"
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: "=&a" (result), "=&a" (tmp)
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: "a" (mask), "a" (v)
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: "memory"
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);
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#else
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unsigned int vval;
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__asm__ __volatile__(
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" rsil a15,"__stringify(LOCKLEVEL)"\n"
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" l32i %0, %2, 0\n"
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" or %0, %0, %1\n"
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" s32i %0, %2, 0\n"
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" wsr a15, ps\n"
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" rsync\n"
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: "=&a" (vval)
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: "a" (mask), "a" (v)
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: "a15", "memory"
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);
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#endif
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}
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/* Atomic operations are already serializing */
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@ -294,4 +396,3 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
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#endif /* __KERNEL__ */
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#endif /* _XTENSA_ATOMIC_H */
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@ -22,17 +22,30 @@
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static inline unsigned long
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__cmpxchg_u32(volatile int *p, int old, int new)
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{
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__asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t"
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"l32i %0, %1, 0 \n\t"
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"bne %0, %2, 1f \n\t"
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"s32i %3, %1, 0 \n\t"
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"1: \n\t"
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"wsr a15, ps \n\t"
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"rsync \n\t"
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: "=&a" (old)
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: "a" (p), "a" (old), "r" (new)
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: "a15", "memory");
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return old;
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#if XCHAL_HAVE_S32C1I
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__asm__ __volatile__(
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" wsr %2, scompare1\n"
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" s32c1i %0, %1, 0\n"
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: "+a" (new)
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: "a" (p), "a" (old)
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: "memory"
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);
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return new;
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#else
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__asm__ __volatile__(
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" rsil a15, "__stringify(LOCKLEVEL)"\n"
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" l32i %0, %1, 0\n"
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" bne %0, %2, 1f\n"
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" s32i %3, %1, 0\n"
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"1:\n"
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" wsr a15, ps\n"
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" rsync\n"
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: "=&a" (old)
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: "a" (p), "a" (old), "r" (new)
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: "a15", "memory");
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return old;
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#endif
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}
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/* This function doesn't exist, so you'll get a linker error
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* if something tries to do an invalid cmpxchg(). */
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@ -93,16 +106,32 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr,
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static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
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{
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unsigned long tmp;
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__asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t"
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"l32i %0, %1, 0 \n\t"
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"s32i %2, %1, 0 \n\t"
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"wsr a15, ps \n\t"
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"rsync \n\t"
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: "=&a" (tmp)
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: "a" (m), "a" (val)
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: "a15", "memory");
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return tmp;
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#if XCHAL_HAVE_S32C1I
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unsigned long tmp, result;
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__asm__ __volatile__(
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"1: l32i %1, %2, 0\n"
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" mov %0, %3\n"
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" wsr %1, scompare1\n"
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" s32c1i %0, %2, 0\n"
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" bne %0, %1, 1b\n"
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: "=&a" (result), "=&a" (tmp)
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: "a" (m), "a" (val)
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: "memory"
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);
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return result;
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#else
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unsigned long tmp;
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__asm__ __volatile__(
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" rsil a15, "__stringify(LOCKLEVEL)"\n"
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" l32i %0, %1, 0\n"
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" s32i %2, %1, 0\n"
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" wsr a15, ps\n"
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" rsync\n"
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: "=&a" (tmp)
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: "a" (m), "a" (val)
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: "a15", "memory");
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return tmp;
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#endif
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}
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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