MIPS: BCM63XX: Add PCIe Support for BCM6328
Add support for the PCIe port found on BCM6328. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Cc: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/3956/ Reviewed-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Jonas Gorski
Ralf Baechle
parent
76f42fe811
commit
19c860d932
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@ -3,6 +3,7 @@ menu "CPU support"
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config BCM63XX_CPU_6328
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bool "support 6328 CPU"
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select HW_HAS_PCI
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config BCM63XX_CPU_6338
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bool "support 6338 CPU"
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@ -122,6 +122,7 @@ enum bcm63xx_regs_set {
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RSET_USBH_PRIV,
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RSET_MPI,
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RSET_PCMCIA,
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RSET_PCIE,
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RSET_DSL,
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RSET_ENET0,
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RSET_ENET1,
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@ -188,6 +189,7 @@ enum bcm63xx_regs_set {
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#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6328_MPI_BASE (0xdeadbeef)
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#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
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#define BCM_6328_PCIE_BASE (0xb0e40000)
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#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
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#define BCM_6328_DSL_BASE (0xb0001900)
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#define BCM_6328_UBUS_BASE (0xdeadbeef)
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@ -232,6 +234,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6338_MPI_BASE (0xfffe3160)
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#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
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#define BCM_6338_PCIE_BASE (0xdeadbeef)
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#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
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#define BCM_6338_DSL_BASE (0xfffe1000)
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#define BCM_6338_UBUS_BASE (0xdeadbeef)
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@ -279,6 +282,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_ENETSW_BASE (0xdeadbeef)
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#define BCM_6345_PCMCIA_BASE (0xfffe2028)
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#define BCM_6345_MPI_BASE (0xfffe2000)
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#define BCM_6345_PCIE_BASE (0xdeadbeef)
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#define BCM_6345_OHCI0_BASE (0xfffe2100)
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#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
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#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
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@ -320,6 +324,7 @@ enum bcm63xx_regs_set {
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#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6348_MPI_BASE (0xfffe2000)
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#define BCM_6348_PCMCIA_BASE (0xfffe2054)
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#define BCM_6348_PCIE_BASE (0xdeadbeef)
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#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6348_M2M_BASE (0xfffe2800)
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#define BCM_6348_DSL_BASE (0xfffe3000)
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@ -362,6 +367,7 @@ enum bcm63xx_regs_set {
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#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
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#define BCM_6358_MPI_BASE (0xfffe1000)
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#define BCM_6358_PCMCIA_BASE (0xfffe1054)
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#define BCM_6358_PCIE_BASE (0xdeadbeef)
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#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6358_M2M_BASE (0xdeadbeef)
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#define BCM_6358_DSL_BASE (0xfffe3000)
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@ -405,6 +411,7 @@ enum bcm63xx_regs_set {
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#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
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#define BCM_6368_MPI_BASE (0xb0001000)
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#define BCM_6368_PCMCIA_BASE (0xb0001054)
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#define BCM_6368_PCIE_BASE (0xdeadbeef)
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#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
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#define BCM_6368_M2M_BASE (0xdeadbeef)
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#define BCM_6368_DSL_BASE (0xdeadbeef)
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@ -453,6 +460,7 @@ extern const unsigned long *bcm63xx_regs_base;
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__GEN_RSET_BASE(__cpu, USBH_PRIV) \
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__GEN_RSET_BASE(__cpu, MPI) \
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__GEN_RSET_BASE(__cpu, PCMCIA) \
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__GEN_RSET_BASE(__cpu, PCIE) \
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__GEN_RSET_BASE(__cpu, DSL) \
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__GEN_RSET_BASE(__cpu, ENET0) \
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__GEN_RSET_BASE(__cpu, ENET1) \
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@ -493,6 +501,7 @@ extern const unsigned long *bcm63xx_regs_base;
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[RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
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[RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
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[RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
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[RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \
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[RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
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[RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
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[RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
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@ -40,6 +40,10 @@
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#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
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BCM_CB_MEM_SIZE - 1)
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#define BCM_PCIE_MEM_BASE_PA 0x10f00000
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#define BCM_PCIE_MEM_SIZE (16 * 1024 * 1024)
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#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \
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BCM_PCIE_MEM_SIZE - 1)
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/*
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* Internal registers are accessed through KSEG3
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@ -85,6 +89,8 @@
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#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o))
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#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o))
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#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
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#define bcm_pcie_readl(o) bcm_rset_readl(RSET_PCIE, (o))
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#define bcm_pcie_writel(v, o) bcm_rset_writel(RSET_PCIE, (v), (o))
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#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o))
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#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
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#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o))
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@ -1162,6 +1162,9 @@
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/*************************************************************************
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* _REG relative to RSET_MISC
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*************************************************************************/
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#define MISC_SERDES_CTRL_REG 0x0
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#define SERDES_PCIE_EN (1 << 0)
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#define SERDES_PCIE_EXD_EN (1 << 15)
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#define MISC_STRAPBUS_6328_REG 0x240
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#define STRAPBUS_6328_FCVO_SHIFT 7
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@ -1169,4 +1172,55 @@
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#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
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#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
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/*************************************************************************
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* _REG relative to RSET_PCIE
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*************************************************************************/
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#define PCIE_CONFIG2_REG 0x408
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#define CONFIG2_BAR1_SIZE_EN 1
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#define CONFIG2_BAR1_SIZE_MASK 0xf
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#define PCIE_IDVAL3_REG 0x43c
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#define IDVAL3_CLASS_CODE_MASK 0xffffff
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#define IDVAL3_SUBCLASS_SHIFT 8
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#define IDVAL3_CLASS_SHIFT 16
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#define PCIE_DLSTATUS_REG 0x1048
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#define DLSTATUS_PHYLINKUP (1 << 13)
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#define PCIE_BRIDGE_OPT1_REG 0x2820
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#define OPT1_RD_BE_OPT_EN (1 << 7)
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#define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
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#define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
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#define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
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#define PCIE_BRIDGE_OPT2_REG 0x2824
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#define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
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#define OPT2_TX_CREDIT_CHK_EN (1 << 4)
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#define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
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#define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
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#define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
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#define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
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#define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
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#define BASEMASK_REMAP_EN (1 << 0)
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#define BASEMASK_SWAP_EN (1 << 1)
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#define BASEMASK_MASK_SHIFT 4
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#define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
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#define BASEMASK_BASE_SHIFT 20
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#define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
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#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
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#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
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#define REBASE_ADDR_BASE_SHIFT 20
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#define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
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#define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
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#define PCIE_RC_INT_A (1 << 0)
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#define PCIE_RC_INT_B (1 << 1)
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#define PCIE_RC_INT_C (1 << 2)
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#define PCIE_RC_INT_D (1 << 3)
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#define PCIE_DEVICE_OFFSET 0x8000
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#endif /* BCM63XX_REGS_H_ */
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@ -465,3 +465,64 @@ static void bcm63xx_fixup(struct pci_dev *dev)
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DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
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#endif
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static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
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{
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switch (bus->number) {
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case PCIE_BUS_BRIDGE:
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return (PCI_SLOT(devfn) == 0);
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case PCIE_BUS_DEVICE:
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if (PCI_SLOT(devfn) == 0)
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return bcm_pcie_readl(PCIE_DLSTATUS_REG)
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& DLSTATUS_PHYLINKUP;
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default:
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return false;
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}
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}
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static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u32 data;
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u32 reg = where & ~3;
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if (!bcm63xx_pcie_can_access(bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (bus->number == PCIE_BUS_DEVICE)
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reg += PCIE_DEVICE_OFFSET;
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data = bcm_pcie_readl(reg);
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*val = postprocess_read(data, where, size);
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return PCIBIOS_SUCCESSFUL;
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}
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static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data;
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u32 reg = where & ~3;
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if (!bcm63xx_pcie_can_access(bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (bus->number == PCIE_BUS_DEVICE)
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reg += PCIE_DEVICE_OFFSET;
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data = bcm_pcie_readl(reg);
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data = preprocess_write(data, val, where, size);
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bcm_pcie_writel(data, reg);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops bcm63xx_pcie_ops = {
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.read = bcm63xx_pcie_read,
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.write = bcm63xx_pcie_write
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};
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@ -10,6 +10,7 @@
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <asm/bootinfo.h>
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#include "pci-bcm63xx.h"
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@ -71,6 +72,26 @@ struct pci_controller bcm63xx_cb_controller = {
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};
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#endif
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static struct resource bcm_pcie_mem_resource = {
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.name = "bcm63xx PCIe memory space",
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.start = BCM_PCIE_MEM_BASE_PA,
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.end = BCM_PCIE_MEM_END_PA,
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.flags = IORESOURCE_MEM,
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};
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static struct resource bcm_pcie_io_resource = {
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.name = "bcm63xx PCIe IO space",
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.start = 0,
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.end = 0,
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.flags = 0,
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};
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struct pci_controller bcm63xx_pcie_controller = {
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.pci_ops = &bcm63xx_pcie_ops,
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.io_resource = &bcm_pcie_io_resource,
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.mem_resource = &bcm_pcie_mem_resource,
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};
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static u32 bcm63xx_int_cfg_readl(u32 reg)
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{
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u32 tmp;
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@ -94,6 +115,95 @@ static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
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void __iomem *pci_iospace_start;
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static void __init bcm63xx_reset_pcie(void)
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{
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u32 val;
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/* enable clock */
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val = bcm_perf_readl(PERF_CKCTL_REG);
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val |= CKCTL_6328_PCIE_EN;
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bcm_perf_writel(val, PERF_CKCTL_REG);
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/* enable SERDES */
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val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
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val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
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bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
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/* reset the PCIe core */
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val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
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val &= ~SOFTRESET_6328_PCIE_MASK;
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val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
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val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
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val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
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bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
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mdelay(10);
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val |= SOFTRESET_6328_PCIE_MASK;
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val |= SOFTRESET_6328_PCIE_CORE_MASK;
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val |= SOFTRESET_6328_PCIE_HARD_MASK;
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bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
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mdelay(10);
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val |= SOFTRESET_6328_PCIE_EXT_MASK;
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bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
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mdelay(200);
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}
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static int __init bcm63xx_register_pcie(void)
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{
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u32 val;
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bcm63xx_reset_pcie();
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/* configure the PCIe bridge */
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val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
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val |= OPT1_RD_BE_OPT_EN;
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val |= OPT1_RD_REPLY_BE_FIX_EN;
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val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
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val |= OPT1_L1_INT_STATUS_MASK_POL;
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bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
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/* setup the interrupts */
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val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
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val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
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bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
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val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
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/* enable credit checking and error checking */
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val |= OPT2_TX_CREDIT_CHK_EN;
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val |= OPT2_UBUS_UR_DECODE_DIS;
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/* set device bus/func for the pcie device */
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val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
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val |= OPT2_CFG_TYPE1_BD_SEL;
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bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
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/* setup class code as bridge */
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val = bcm_pcie_readl(PCIE_IDVAL3_REG);
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val &= ~IDVAL3_CLASS_CODE_MASK;
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val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
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bcm_pcie_writel(val, PCIE_IDVAL3_REG);
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/* disable bar1 size */
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val = bcm_pcie_readl(PCIE_CONFIG2_REG);
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val &= ~CONFIG2_BAR1_SIZE_MASK;
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bcm_pcie_writel(val, PCIE_CONFIG2_REG);
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/* set bar0 to little endian */
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val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
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val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
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val |= BASEMASK_REMAP_EN;
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bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
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val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
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bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
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register_pci_controller(&bcm63xx_pcie_controller);
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return 0;
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}
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static int __init bcm63xx_register_pci(void)
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{
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unsigned int mem_size;
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@ -221,6 +331,8 @@ static int __init bcm63xx_pci_init(void)
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return -ENODEV;
|
||||
|
||||
switch (bcm63xx_get_cpu_id()) {
|
||||
case BCM6328_CPU_ID:
|
||||
return bcm63xx_register_pcie();
|
||||
case BCM6348_CPU_ID:
|
||||
case BCM6358_CPU_ID:
|
||||
case BCM6368_CPU_ID:
|
||||
|
|
|
|||
|
|
@ -13,11 +13,16 @@
|
|||
*/
|
||||
#define CARDBUS_PCI_IDSEL 0x8
|
||||
|
||||
|
||||
#define PCIE_BUS_BRIDGE 0
|
||||
#define PCIE_BUS_DEVICE 1
|
||||
|
||||
/*
|
||||
* defined in ops-bcm63xx.c
|
||||
*/
|
||||
extern struct pci_ops bcm63xx_pci_ops;
|
||||
extern struct pci_ops bcm63xx_cb_ops;
|
||||
extern struct pci_ops bcm63xx_pcie_ops;
|
||||
|
||||
/*
|
||||
* defined in pci-bcm63xx.c
|
||||
|
|
|
|||
Reference in New Issue