rtc: snvs: add Freescale rtc-snvs driver
Add an RTC driver for Freescale Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Kim Phillips <kim.phillips@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Shawn Guo
Linus Torvalds
parent
7418a11989
commit
179a502f8c
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@ -9,6 +9,7 @@ Copyright (C) 2008-2011 Freescale Semiconductor Inc.
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-Run Time Integrity Check (RTIC) Node
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-Run Time Integrity Check (RTIC) Memory Node
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-Secure Non-Volatile Storage (SNVS) Node
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-Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
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-Full Example
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NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
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@ -294,6 +295,27 @@ Secure Non-Volatile Storage (SNVS) Node
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address and length of the SEC4 configuration
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registers.
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- #address-cells
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Usage: required
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Value type: <u32>
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Definition: A standard property. Defines the number of cells
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for representing physical addresses in child nodes. Must
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have a value of 1.
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- #size-cells
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Usage: required
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Value type: <u32>
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Definition: A standard property. Defines the number of cells
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for representing the size of physical addresses in
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child nodes. Must have a value of 1.
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- ranges
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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range of the SNVS register space. A triplet that includes
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the child address, parent address, & length.
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- interrupts
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Usage: required
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Value type: <prop_encoded-array>
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@ -314,10 +336,33 @@ EXAMPLE
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sec_mon@314000 {
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compatible = "fsl,sec-v4.0-mon";
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reg = <0x314000 0x1000>;
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ranges = <0 0x314000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <93 2>;
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};
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=====================================================================
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Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
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A SNVS child node that defines SNVS LP RTC.
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical
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address and length of the SNVS LP configuration registers.
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EXAMPLE
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sec_mon_rtc_lp@314000 {
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compatible = "fsl,sec-v4.0-mon-rtc-lp";
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reg = <0x34 0x58>;
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};
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=====================================================================
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FULL EXAMPLE
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@ -390,8 +435,14 @@ FULL EXAMPLE
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sec_mon: sec_mon@314000 {
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compatible = "fsl,sec-v4.0-mon";
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reg = <0x314000 0x1000>;
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ranges = <0 0x314000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <93 2>;
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sec_mon_rtc_lp@34 {
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compatible = "fsl,sec-v4.0-mon-rtc-lp";
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reg = <0x34 0x58>;
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};
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};
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=====================================================================
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@ -0,0 +1 @@
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See Documentation/devicetree/bindings/crypto/fsl-sec4.txt for details.
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@ -1109,4 +1109,15 @@ config RTC_DRV_MXC
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This driver can also be built as a module, if so, the module
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will be called "rtc-mxc".
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config RTC_DRV_SNVS
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tristate "Freescale SNVS RTC support"
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depends on HAS_IOMEM
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depends on OF
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help
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If you say yes here you get support for the Freescale SNVS
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Low Power (LP) RTC module.
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This driver can also be built as a module, if so, the module
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will be called "rtc-snvs".
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endif # RTC_CLASS
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@ -97,6 +97,7 @@ obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o
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obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o
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obj-$(CONFIG_RTC_DRV_SA1100) += rtc-sa1100.o
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obj-$(CONFIG_RTC_DRV_SH) += rtc-sh.o
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obj-$(CONFIG_RTC_DRV_SNVS) += rtc-snvs.o
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obj-$(CONFIG_RTC_DRV_SPEAR) += rtc-spear.o
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obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-starfire.o
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obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o
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@ -0,0 +1,350 @@
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/*
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* Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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/* These register offsets are relative to LP (Low Power) range */
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#define SNVS_LPCR 0x04
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#define SNVS_LPSR 0x18
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#define SNVS_LPSRTCMR 0x1c
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#define SNVS_LPSRTCLR 0x20
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#define SNVS_LPTAR 0x24
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#define SNVS_LPPGDR 0x30
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#define SNVS_LPCR_SRTC_ENV (1 << 0)
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#define SNVS_LPCR_LPTA_EN (1 << 1)
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#define SNVS_LPCR_LPWUI_EN (1 << 3)
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#define SNVS_LPSR_LPTA (1 << 0)
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#define SNVS_LPPGDR_INIT 0x41736166
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#define CNTR_TO_SECS_SH 15
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struct snvs_rtc_data {
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struct rtc_device *rtc;
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void __iomem *ioaddr;
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int irq;
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spinlock_t lock;
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};
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static u32 rtc_read_lp_counter(void __iomem *ioaddr)
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{
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u64 read1, read2;
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do {
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read1 = readl(ioaddr + SNVS_LPSRTCMR);
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read1 <<= 32;
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read1 |= readl(ioaddr + SNVS_LPSRTCLR);
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read2 = readl(ioaddr + SNVS_LPSRTCMR);
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read2 <<= 32;
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read2 |= readl(ioaddr + SNVS_LPSRTCLR);
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} while (read1 != read2);
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/* Convert 47-bit counter to 32-bit raw second count */
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return (u32) (read1 >> CNTR_TO_SECS_SH);
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}
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static void rtc_write_sync_lp(void __iomem *ioaddr)
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{
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u32 count1, count2, count3;
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int i;
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/* Wait for 3 CKIL cycles */
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for (i = 0; i < 3; i++) {
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do {
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count1 = readl(ioaddr + SNVS_LPSRTCLR);
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count2 = readl(ioaddr + SNVS_LPSRTCLR);
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} while (count1 != count2);
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/* Now wait until counter value changes */
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do {
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do {
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count2 = readl(ioaddr + SNVS_LPSRTCLR);
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count3 = readl(ioaddr + SNVS_LPSRTCLR);
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} while (count2 != count3);
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} while (count3 == count1);
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}
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}
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static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
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{
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unsigned long flags;
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int timeout = 1000;
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u32 lpcr;
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spin_lock_irqsave(&data->lock, flags);
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lpcr = readl(data->ioaddr + SNVS_LPCR);
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if (enable)
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lpcr |= SNVS_LPCR_SRTC_ENV;
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else
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lpcr &= ~SNVS_LPCR_SRTC_ENV;
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writel(lpcr, data->ioaddr + SNVS_LPCR);
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spin_unlock_irqrestore(&data->lock, flags);
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while (--timeout) {
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lpcr = readl(data->ioaddr + SNVS_LPCR);
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if (enable) {
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if (lpcr & SNVS_LPCR_SRTC_ENV)
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break;
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} else {
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if (!(lpcr & SNVS_LPCR_SRTC_ENV))
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break;
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}
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}
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if (!timeout)
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return -ETIMEDOUT;
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return 0;
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}
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static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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unsigned long time = rtc_read_lp_counter(data->ioaddr);
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rtc_time_to_tm(time, tm);
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return 0;
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}
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static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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unsigned long time;
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rtc_tm_to_time(tm, &time);
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/* Disable RTC first */
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snvs_rtc_enable(data, false);
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/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
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writel(time << CNTR_TO_SECS_SH, data->ioaddr + SNVS_LPSRTCLR);
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writel(time >> (32 - CNTR_TO_SECS_SH), data->ioaddr + SNVS_LPSRTCMR);
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/* Enable RTC again */
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snvs_rtc_enable(data, true);
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return 0;
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}
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static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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u32 lptar, lpsr;
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lptar = readl(data->ioaddr + SNVS_LPTAR);
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rtc_time_to_tm(lptar, &alrm->time);
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lpsr = readl(data->ioaddr + SNVS_LPSR);
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alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
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return 0;
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}
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static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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u32 lpcr;
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unsigned long flags;
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spin_lock_irqsave(&data->lock, flags);
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lpcr = readl(data->ioaddr + SNVS_LPCR);
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if (enable)
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lpcr |= (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
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else
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lpcr &= ~(SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
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writel(lpcr, data->ioaddr + SNVS_LPCR);
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spin_unlock_irqrestore(&data->lock, flags);
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rtc_write_sync_lp(data->ioaddr);
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return 0;
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}
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static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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struct rtc_time *alrm_tm = &alrm->time;
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unsigned long time;
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unsigned long flags;
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u32 lpcr;
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rtc_tm_to_time(alrm_tm, &time);
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spin_lock_irqsave(&data->lock, flags);
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/* Have to clear LPTA_EN before programming new alarm time in LPTAR */
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lpcr = readl(data->ioaddr + SNVS_LPCR);
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lpcr &= ~SNVS_LPCR_LPTA_EN;
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writel(lpcr, data->ioaddr + SNVS_LPCR);
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spin_unlock_irqrestore(&data->lock, flags);
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writel(time, data->ioaddr + SNVS_LPTAR);
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/* Clear alarm interrupt status bit */
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writel(SNVS_LPSR_LPTA, data->ioaddr + SNVS_LPSR);
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return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
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}
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static const struct rtc_class_ops snvs_rtc_ops = {
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.read_time = snvs_rtc_read_time,
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.set_time = snvs_rtc_set_time,
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.read_alarm = snvs_rtc_read_alarm,
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.set_alarm = snvs_rtc_set_alarm,
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.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
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};
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static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
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{
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struct device *dev = dev_id;
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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u32 lpsr;
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u32 events = 0;
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lpsr = readl(data->ioaddr + SNVS_LPSR);
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if (lpsr & SNVS_LPSR_LPTA) {
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events |= (RTC_AF | RTC_IRQF);
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/* RTC alarm should be one-shot */
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snvs_rtc_alarm_irq_enable(dev, 0);
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rtc_update_irq(data->rtc, 1, events);
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}
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/* clear interrupt status */
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writel(lpsr, data->ioaddr + SNVS_LPSR);
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return events ? IRQ_HANDLED : IRQ_NONE;
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}
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static int __devinit snvs_rtc_probe(struct platform_device *pdev)
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{
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struct snvs_rtc_data *data;
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struct resource *res;
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int ret;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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data->ioaddr = devm_request_and_ioremap(&pdev->dev, res);
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if (!data->ioaddr)
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return -EADDRNOTAVAIL;
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data->irq = platform_get_irq(pdev, 0);
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if (data->irq < 0)
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return data->irq;
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platform_set_drvdata(pdev, data);
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spin_lock_init(&data->lock);
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/* Initialize glitch detect */
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writel(SNVS_LPPGDR_INIT, data->ioaddr + SNVS_LPPGDR);
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/* Clear interrupt status */
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writel(0xffffffff, data->ioaddr + SNVS_LPSR);
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/* Enable RTC */
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snvs_rtc_enable(data, true);
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device_init_wakeup(&pdev->dev, true);
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ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
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IRQF_SHARED, "rtc alarm", &pdev->dev);
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if (ret) {
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dev_err(&pdev->dev, "failed to request irq %d: %d\n",
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data->irq, ret);
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return ret;
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}
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data->rtc = rtc_device_register(pdev->name, &pdev->dev,
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&snvs_rtc_ops, THIS_MODULE);
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if (IS_ERR(data->rtc)) {
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ret = PTR_ERR(data->rtc);
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dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int __devexit snvs_rtc_remove(struct platform_device *pdev)
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{
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struct snvs_rtc_data *data = platform_get_drvdata(pdev);
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rtc_device_unregister(data->rtc);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int snvs_rtc_suspend(struct device *dev)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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enable_irq_wake(data->irq);
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return 0;
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}
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static int snvs_rtc_resume(struct device *dev)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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disable_irq_wake(data->irq);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(snvs_rtc_pm_ops, snvs_rtc_suspend, snvs_rtc_resume);
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static const struct of_device_id __devinitconst snvs_dt_ids[] = {
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{ .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, snvs_dt_ids);
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static struct platform_driver snvs_rtc_driver = {
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.driver = {
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.name = "snvs_rtc",
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.owner = THIS_MODULE,
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.pm = &snvs_rtc_pm_ops,
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.of_match_table = snvs_dt_ids,
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},
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.probe = snvs_rtc_probe,
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.remove = __devexit_p(snvs_rtc_remove),
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};
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module_platform_driver(snvs_rtc_driver);
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MODULE_AUTHOR("Freescale Semiconductor, Inc.");
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MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
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MODULE_LICENSE("GPL");
|
||||
Reference in New Issue