sh: Add support for SH7723 CPU subtype.
This adds basic support for the SH7723 MobileR2 CPU. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
47aa8f493f
commit
178dd0cd28
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@ -276,6 +276,15 @@ config CPU_SUBTYPE_SH4_202
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# SH-4A Processor Support
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config CPU_SUBTYPE_SH7723
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bool "Support SH7723 processor"
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select CPU_SH4A
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select CPU_SHX2
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select ARCH_SPARSEMEM_ENABLE
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select SYS_SUPPORTS_NUMA
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help
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Select SH7723 if you have an SH-MobileR2 CPU.
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config CPU_SUBTYPE_SH7763
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bool "Support SH7763 processor"
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select CPU_SH4A
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@ -600,7 +609,7 @@ config SH_PCLK_FREQ
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default "27000000" if CPU_SUBTYPE_SH7343
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default "31250000" if CPU_SUBTYPE_SH7619
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default "32000000" if CPU_SUBTYPE_SH7722
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default "33333333" if CPU_SUBTYPE_SH7770 || \
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default "33333333" if CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7723 || \
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CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
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CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
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CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG
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@ -126,17 +126,22 @@ int __init detect_cpu_and_cache_system(void)
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CPU_HAS_LLSC;
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break;
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case 0x3008:
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if (prr == 0xa0 || prr == 0xa1) {
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boot_cpu_data.type = CPU_SH7722;
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boot_cpu_data.icache.ways = 4;
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boot_cpu_data.dcache.ways = 4;
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boot_cpu_data.flags |= CPU_HAS_LLSC;
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}
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else if (prr == 0x70) {
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boot_cpu_data.icache.ways = 4;
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boot_cpu_data.dcache.ways = 4;
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boot_cpu_data.flags |= CPU_HAS_LLSC;
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switch (prr) {
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case 0x50:
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boot_cpu_data.type = CPU_SH7723;
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boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE;
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break;
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case 0x70:
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boot_cpu_data.type = CPU_SH7366;
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boot_cpu_data.icache.ways = 4;
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boot_cpu_data.dcache.ways = 4;
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boot_cpu_data.flags |= CPU_HAS_LLSC;
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break;
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case 0xa0:
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case 0xa1:
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boot_cpu_data.type = CPU_SH7722;
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break;
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}
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break;
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case 0x4000: /* 1st cut */
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@ -9,6 +9,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
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obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
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@ -22,6 +23,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o
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clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
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@ -0,0 +1,300 @@
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/*
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* SH7723 Setup
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*
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* Copyright (C) 2008 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/mm.h>
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#include <linux/serial_sci.h>
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#include <asm/mmzone.h>
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xa4e30000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCI,
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.irqs = { 56, 56, 56, 56 },
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},{
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.mapbase = 0xa4e40000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCI,
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.irqs = { 88, 88, 88, 88 },
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},{
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.mapbase = 0xa4e50000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCI,
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.irqs = { 109, 109, 109, 109 },
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}, {
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.flags = 0,
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}
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};
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static struct platform_device sci_device = {
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.name = "sh-sci",
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.id = -1,
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.dev = {
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.platform_data = sci_platform_data,
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},
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};
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static struct resource rtc_resources[] = {
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[0] = {
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.start = 0xa465fec0,
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.end = 0xa465fec0 + 0x58 - 1,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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/* Period IRQ */
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.start = 69,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* Carry IRQ */
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.start = 70,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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/* Alarm IRQ */
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.start = 68,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device rtc_device = {
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.name = "sh-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(rtc_resources),
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.resource = rtc_resources,
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};
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static struct platform_device *sh7723_devices[] __initdata = {
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&sci_device,
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&rtc_device,
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};
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static int __init sh7723_devices_setup(void)
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{
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return platform_add_devices(sh7723_devices,
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ARRAY_SIZE(sh7723_devices));
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}
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__initcall(sh7723_devices_setup);
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enum {
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UNUSED=0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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HUDI,
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DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
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_2DG_TRI,_2DG_INI,_2DG_CEI,
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DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
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VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
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SCIFA_SCIFA0,
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VPU_VPUI,
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TPU_TPUI,
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ADC_ADI,
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USB_USI0,
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RTC_ATI,RTC_PRI,RTC_CUI,
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DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
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DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
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KEYSC_KEYI,
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SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
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MSIOF_MSIOFI0,MSIOF_MSIOFI1,
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SCIFA_SCIFA1,
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FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
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I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
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SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
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CMT_CMTI,
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TSIF_TSIFI,
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SIU_SIUI,
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SCIFA_SCIFA2,
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TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
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IRDA_IRDAI,
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ATAPI_ATAPII,
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SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
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VEU2H1_VEU2HI,
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LCDC_LCDCI,
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TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
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/* interrupt groups */
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DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
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SDHI1, RTC, DMAC1B, SDHI0,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
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INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
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INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
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INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
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INTC_VECT(DMAC1A_DEI0,0x700),
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INTC_VECT(DMAC1A_DEI1,0x720),
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INTC_VECT(DMAC1A_DEI2,0x740),
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INTC_VECT(DMAC1A_DEI3,0x760),
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INTC_VECT(_2DG_TRI, 0x780),
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INTC_VECT(_2DG_INI, 0x7A0),
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INTC_VECT(_2DG_CEI, 0x7C0),
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INTC_VECT(DMAC0A_DEI0,0x800),
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INTC_VECT(DMAC0A_DEI1,0x820),
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INTC_VECT(DMAC0A_DEI2,0x840),
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INTC_VECT(DMAC0A_DEI3,0x860),
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INTC_VECT(VIO_CEUI,0x880),
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INTC_VECT(VIO_BEUI,0x8A0),
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INTC_VECT(VIO_VEU2HI,0x8C0),
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INTC_VECT(VIO_VOUI,0x8E0),
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INTC_VECT(SCIFA_SCIFA0,0x900),
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INTC_VECT(VPU_VPUI,0x920),
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INTC_VECT(TPU_TPUI,0x9A0),
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INTC_VECT(ADC_ADI,0x9E0),
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INTC_VECT(USB_USI0,0xA20),
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INTC_VECT(RTC_ATI,0xA80),
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INTC_VECT(RTC_PRI,0xAA0),
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INTC_VECT(RTC_CUI,0xAC0),
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INTC_VECT(DMAC1B_DEI4,0xB00),
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INTC_VECT(DMAC1B_DEI5,0xB20),
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INTC_VECT(DMAC1B_DADERR,0xB40),
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INTC_VECT(DMAC0B_DEI4,0xB80),
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INTC_VECT(DMAC0B_DEI5,0xBA0),
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INTC_VECT(DMAC0B_DADERR,0xBC0),
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INTC_VECT(KEYSC_KEYI,0xBE0),
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INTC_VECT(SCIF_SCIF0,0xC00),
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INTC_VECT(SCIF_SCIF1,0xC20),
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INTC_VECT(SCIF_SCIF2,0xC40),
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INTC_VECT(MSIOF_MSIOFI0,0xC80),
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INTC_VECT(MSIOF_MSIOFI1,0xCA0),
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INTC_VECT(SCIFA_SCIFA1,0xD00),
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INTC_VECT(FLCTL_FLSTEI,0xD80),
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INTC_VECT(FLCTL_FLTENDI,0xDA0),
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INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
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INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
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INTC_VECT(I2C_ALI,0xE00),
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INTC_VECT(I2C_TACKI,0xE20),
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INTC_VECT(I2C_WAITI,0xE40),
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INTC_VECT(I2C_DTEI,0xE60),
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INTC_VECT(SDHI0_SDHII0,0xE80),
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INTC_VECT(SDHI0_SDHII1,0xEA0),
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INTC_VECT(SDHI0_SDHII2,0xEC0),
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INTC_VECT(CMT_CMTI,0xF00),
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INTC_VECT(TSIF_TSIFI,0xF20),
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INTC_VECT(SIU_SIUI,0xF80),
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INTC_VECT(SCIFA_SCIFA2,0xFA0),
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INTC_VECT(TMU0_TUNI0,0x400),
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INTC_VECT(TMU0_TUNI1,0x420),
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INTC_VECT(TMU0_TUNI2,0x440),
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INTC_VECT(IRDA_IRDAI,0x480),
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INTC_VECT(ATAPI_ATAPII,0x4A0),
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INTC_VECT(SDHI1_SDHII0,0x4E0),
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INTC_VECT(SDHI1_SDHII1,0x500),
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INTC_VECT(SDHI1_SDHII2,0x520),
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INTC_VECT(VEU2H1_VEU2HI,0x560),
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INTC_VECT(LCDC_LCDCI,0x580),
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INTC_VECT(TMU1_TUNI0,0x920),
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INTC_VECT(TMU1_TUNI1,0x940),
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INTC_VECT(TMU1_TUNI2,0x960),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
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INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
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INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
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INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
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INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
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INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
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INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
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INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
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INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
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INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
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INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
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{ 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
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{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
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{ VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
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{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
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{ 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
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{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
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{ DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
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{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
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{ 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
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{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
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{ KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
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{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
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{ 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
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{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
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{ I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
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FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
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{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
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{ 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
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{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
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{ 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
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{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
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{ 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
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{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
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{ 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
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{ 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
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{ 0,0,0,0,0,0,0,ATAPI_ATAPII } },
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{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
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{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
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{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
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{ 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
|
||||
{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
|
||||
{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
|
||||
{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
|
||||
{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
|
||||
{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
|
||||
{ 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
|
||||
{ 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
|
||||
{ 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
|
||||
{ 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
|
||||
{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
|
||||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static struct intc_sense_reg sense_registers[] __initdata = {
|
||||
{ 0xa414001c, 16, 2, /* ICR1 */
|
||||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7723", vectors, groups,
|
||||
mask_registers, prio_registers, sense_registers);
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
/* Register the URAM space as Node 1 */
|
||||
setup_bootmem_node(1, 0x055f0000, 0x05610000);
|
||||
}
|
||||
|
|
@ -335,7 +335,7 @@ static const char *cpu_name[] = {
|
|||
[CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
|
||||
[CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
|
||||
[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
|
||||
[CPU_MXG] = "MX-G",
|
||||
[CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
|
||||
[CPU_SH7366] = "SH7366", [CPU_SH_NONE] = "Unknown"
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -333,7 +333,6 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
|||
}
|
||||
sci_out(port, SCFCR, fcr_val);
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_CPU_SH3)
|
||||
/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
|
||||
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
||||
|
|
@ -384,6 +383,12 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
|||
|
||||
sci_out(port, SCFCR, fcr_val);
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
|
||||
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
||||
{
|
||||
/* Nothing to do here.. */
|
||||
sci_out(port, SCFCR, 0);
|
||||
}
|
||||
#else
|
||||
/* For SH7750 */
|
||||
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
||||
|
|
|
|||
|
|
@ -1,20 +1,5 @@
|
|||
/* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
|
||||
*
|
||||
* linux/drivers/serial/sh-sci.h
|
||||
*
|
||||
* SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
|
||||
* Copyright (C) 1999, 2000 Niibe Yutaka
|
||||
* Copyright (C) 2000 Greg Banks
|
||||
* Copyright (C) 2002, 2003 Paul Mundt
|
||||
* Modified to support multiple serial ports. Stuart Menefy (May 2000).
|
||||
* Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
|
||||
* Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
|
||||
* Removed SH7300 support (Jul 2007).
|
||||
* Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Aug 2007).
|
||||
*/
|
||||
#include <linux/serial_core.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <asm/gpio.h>
|
||||
|
||||
#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
|
||||
|
|
@ -102,6 +87,15 @@
|
|||
# define SCSPTR0 SCPDR0
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
|
||||
# define SCSPTR0 0xa4050160
|
||||
# define SCSPTR1 0xa405013e
|
||||
# define SCSPTR2 0xa4050160
|
||||
# define SCSPTR3 0xa405013e
|
||||
# define SCSPTR4 0xa4050128
|
||||
# define SCSPTR5 0xa4050128
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
|
||||
# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
|
||||
|
|
@ -395,6 +389,11 @@
|
|||
h8_sci_offset, h8_sci_size) \
|
||||
CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
|
||||
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
|
||||
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
|
||||
#define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
||||
#else
|
||||
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
|
||||
sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
|
||||
|
|
@ -419,6 +418,18 @@ SCIF_FNS(SCFDR, 0x1c, 16)
|
|||
SCIF_FNS(SCxTDR, 0x20, 8)
|
||||
SCIF_FNS(SCxRDR, 0x24, 8)
|
||||
SCIF_FNS(SCLSR, 0x24, 16)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
|
||||
SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
|
||||
SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
|
||||
SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
|
||||
SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
|
||||
SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
|
||||
SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
|
||||
SCIF_FNS(SCTDSR, 0x0c, 8)
|
||||
SCIF_FNS(SCFER, 0x10, 16)
|
||||
SCIF_FNS(SCFCR, 0x18, 16)
|
||||
SCIF_FNS(SCFDR, 0x1c, 16)
|
||||
SCIF_FNS(SCLSR, 0x24, 16)
|
||||
#else
|
||||
/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
|
||||
/* name off sz off sz off sz off sz off sz*/
|
||||
|
|
@ -589,6 +600,23 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffe00000)
|
||||
return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
|
||||
if (port->mapbase == 0xffe10000)
|
||||
return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
|
||||
if (port->mapbase == 0xffe20000)
|
||||
return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
|
||||
if (port->mapbase == 0xa4e30000)
|
||||
return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
|
||||
if (port->mapbase == 0xa4e40000)
|
||||
return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
|
||||
if (port->mapbase == 0xa4e50000)
|
||||
return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
|
|
@ -727,6 +755,8 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721)
|
||||
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
|
||||
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(16*bps)-1)
|
||||
#elif defined(__H8300H__) || defined(__H8300S__)
|
||||
#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
|
||||
#elif defined(CONFIG_SUPERH64)
|
||||
|
|
|
|||
|
|
@ -10,14 +10,14 @@
|
|||
#ifndef __ASM_CPU_SH4_FREQ_H
|
||||
#define __ASM_CPU_SH4_FREQ_H
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7366)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7723) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7366)
|
||||
#define FRQCR 0xa4150000
|
||||
#define VCLKCR 0xa4150004
|
||||
#define SCLKACR 0xa4150008
|
||||
#define SCLKBCR 0xa415000c
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7722)
|
||||
#define IrDACLKCR 0xa4150010
|
||||
#endif
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#define FRQCR 0xffc80000
|
||||
|
|
|
|||
|
|
@ -1,7 +1,12 @@
|
|||
#ifndef __ASM_SH_CPU_SH4_RTC_H
|
||||
#define __ASM_SH_CPU_SH4_RTC_H
|
||||
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7723
|
||||
#define rtc_reg_size sizeof(u16)
|
||||
#else
|
||||
#define rtc_reg_size sizeof(u32)
|
||||
#endif
|
||||
|
||||
#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
|
||||
#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,8 @@ enum cpu_type {
|
|||
CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
|
||||
|
||||
/* SH-4A types */
|
||||
CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
|
||||
CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
|
||||
CPU_SH7723, CPU_SHX3,
|
||||
|
||||
/* SH4AL-DSP types */
|
||||
CPU_SH7343, CPU_SH7722, CPU_SH7366,
|
||||
|
|
|
|||
Reference in New Issue