dect: coa: support operation on all slots
Support operation on uneven slot numbers. The firmware is rewritten to follow the following scheme: - each slot has an entry in the SlotTable consisting of two intructions - idle slots use WT 1 + WNT 1 - for active slots the previous slot is programmed to switch to the proper memory bank and initialize the BMC/radio - the actual slot is programmed to jump to one the receive or transmit functions The transceiver layer takes care of scheduling operation only on slots that are surrounded by idle slots based on the DECT_TRANSCEIVER_SLOW_HOPPING feature flag. Signed-off-by: Patrick McHardy <kaber@trash.net>
This commit is contained in:
parent
2bcb0143d1
commit
16faf2d44c
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@ -224,6 +224,9 @@
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#define SC1442X_CC0_STANDBY 0xc2
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#define SC1442X_CC0_POWERDOWN 0x3d
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/* Logical memory banks */
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#define SC1442X_BANK_UNITS 8
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#define SC1442X_SLOT_BANK_SIZE 128
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static const u8 banktable[] = {
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SC1442X_RAMBANK1,
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@ -234,34 +237,10 @@ static const u8 banktable[] = {
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SC1442X_RAMBANK6,
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};
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static const u8 jumptable[] = {
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JP0, 0,
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JP2, 0,
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JP4, 0,
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JP6, 0,
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JP8, 0,
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JP10, 0,
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JP12, 0,
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JP14, 0,
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JP16, 0,
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JP18, 0,
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JP20, 0,
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JP22, 0
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};
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static const u8 patchtable[] = {
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PP0, 0,
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PP2, 0,
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PP4, 0,
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PP6, 0,
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PP8, 0,
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PP10, 0,
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PP12, 0,
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PP14, 0,
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PP16, 0,
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PP18, 0,
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PP20, 0,
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PP22, 0
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static const u8 slottable[] = {
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Slot00, Slot01, Slot02, Slot03, Slot04, Slot05, Slot06, Slot07,
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Slot08, Slot09, Slot10, Slot11, Slot12, Slot13, Slot14, Slot15,
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Slot16, Slot17, Slot18, Slot19, Slot20, Slot21, Slot22, Slot23,
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};
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static const u8 sc1442x_rx_funcs[DECT_PACKET_MAX + 1][DECT_B_MAX + 1][2][2] = {
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@ -454,6 +433,11 @@ static void sc1442x_from_dmem(const struct coa_device *dev, void *dst,
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*(u8 *)(dst + i) = sc1442x_dreadb(dev, offset + i);
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}
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static u8 sc1442x_dip_bankaddress(u8 slot)
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{
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return (slot / 2 + 2) * SC1442X_SLOT_BANK_SIZE / SC1442X_BANK_UNITS;
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}
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static u8 sc1442x_slot_bank(u8 slot)
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{
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return banktable[slot / 4];
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@ -463,7 +447,6 @@ static u16 sc1442x_slot_offset(u8 slot)
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{
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u16 offset;
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WARN_ON_ONCE(slot & 0x1);
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offset = SC1442X_BANKSIZE + slot / 4 * SC1442X_BANKSIZE;
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if (slot & 0x2)
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offset += SC1442X_BANKSIZE / 2;
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@ -533,8 +516,10 @@ static void sc1442x_enable(const struct dect_transceiver *trx)
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/* Restore slot table to a pristine state */
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sc1442x_switch_to_bank(dev, SC1442X_CODEBANK);
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for (slot = 0; slot < DECT_FRAME_SIZE; slot += 2)
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sc1442x_write_cmd(dev, patchtable[slot], WNT, 2);
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for (slot = 0; slot < DECT_FRAME_SIZE; slot++) {
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sc1442x_write_cmd(dev, slottable[slot] + 0, WT, 1);
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sc1442x_write_cmd(dev, slottable[slot] + 1, WNT, 1);
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}
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if (trx->cell->mode == DECT_MODE_FP) {
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sc1442x_write_cmd(dev, ClockSyncOn, WT, 1);
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@ -599,11 +584,10 @@ static void sc1442x_lock(const struct dect_transceiver *trx, u8 slot)
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* event. This will automagically establish the correct slot numbers
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* and thereby interrupt timing for all slots.
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*/
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WARN_ON_ONCE(slot & 0x1);
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sc1442x_lock_mem(dev);
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sc1442x_switch_to_bank(dev, SC1442X_CODEBANK);
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sc1442x_write_cmd(dev, SlotTable, SLOTZERO, 0);
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sc1442x_write_cmd(dev, SyncLoop, BR, jumptable[slot]);
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sc1442x_write_cmd(dev, SyncLoop, BR, slottable[slot]);
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sc1442x_unlock_mem(dev);
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}
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@ -614,23 +598,33 @@ static void sc1442x_set_mode(const struct dect_transceiver *trx,
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struct coa_device *dev = dect_transceiver_priv(trx);
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bool cipher = trx->slots[chd->slot].flags & DECT_SLOT_CIPHER;
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bool sync = trx->slots[chd->slot].flags & DECT_SLOT_SYNC;
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u8 slot = chd->slot;
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u8 slot = chd->slot, prev = dect_slot_sub(slot, 1);
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WARN_ON_ONCE(slot & 0x1);
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sc1442x_lock_mem(dev);
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sc1442x_switch_to_bank(dev, SC1442X_CODEBANK);
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switch (mode) {
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case DECT_SLOT_IDLE:
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sc1442x_write_cmd(dev, patchtable[slot], WNT, 2);
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sc1442x_write_cmd(dev, slottable[prev] + 0, WT, 1);
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sc1442x_write_cmd(dev, slottable[prev] + 1, WNT, 1);
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sc1442x_write_cmd(dev, slottable[slot] + 0, WT, 1);
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sc1442x_write_cmd(dev, slottable[slot] + 1, WNT, 1);
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break;
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case DECT_SLOT_SCANNING:
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case DECT_SLOT_RX:
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sc1442x_write_cmd(dev, patchtable[slot], JMP,
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sc1442x_write_cmd(dev, slottable[prev] + 0, BK_C,
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sc1442x_dip_bankaddress(slot));
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sc1442x_write_cmd(dev, slottable[prev] + 1, JMP, RFInit);
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sc1442x_write_cmd(dev, slottable[slot] + 0, WT, 1);
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sc1442x_write_cmd(dev, slottable[slot] + 1, JMP,
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sc1442x_rx_funcs[chd->pkt][chd->b_fmt][cipher][sync]);
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break;
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case DECT_SLOT_TX:
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sc1442x_write_cmd(dev, patchtable[slot], JMP,
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sc1442x_write_cmd(dev, slottable[prev] + 0, BK_C,
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sc1442x_dip_bankaddress(slot));
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sc1442x_write_cmd(dev, slottable[prev] + 1, JMP, RFInit);
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sc1442x_write_cmd(dev, slottable[slot] + 0, WT, 1);
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sc1442x_write_cmd(dev, slottable[slot] + 1, JMP,
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sc1442x_tx_funcs[chd->pkt][chd->b_fmt][cipher]);
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break;
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}
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@ -871,7 +865,7 @@ irqreturn_t sc1442x_interrupt(int irq, void *dev_id)
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goto out;
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spin_lock(&dev->lock);
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for (slot = 6 * i; slot < 6 * (i + 1); slot += 2) {
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for (slot = 6 * i; slot < 6 * (i + 1); slot++) {
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sc1442x_process_slot(dev, trx, event, slot);
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if (slot < DECT_HALF_FRAME_SIZE)
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sc1442x_transfer_dcs_state(dev, trx, slot);
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@ -80,36 +80,60 @@ Start: BR InitDIP
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SlotTable: SLOTZERO
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JP0: BK_C BANK1_LOW
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PP0: WNT 2
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JP2: BK_C BANK1_HIGH
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PP2: WNT 2
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JP4: BK_C BANK2_LOW
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PP4: WNT 2
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Slot00: WT 1
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WNT 1
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Slot01: WT 1
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WNT 1
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Slot02: WT 1
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WNT 1
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Slot03: WT 1
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WNT 1
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Slot04: WT 1
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WNT 1
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Slot05: WT 1
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WNT 1
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U_INT0
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JP6: BK_C BANK2_HIGH
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PP6: WNT 2
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JP8: BK_C BANK3_LOW
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PP8: WNT 2
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JP10: BK_C BANK3_HIGH
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PP10: WNT 2
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Slot06: WT 1
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WNT 1
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Slot07: WT 1
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WNT 1
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Slot08: WT 1
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WNT 1
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Slot09: WT 1
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WNT 1
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Slot10: WT 1
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WNT 1
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Slot11: WT 1
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WNT 1
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U_INT1
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JP12: BK_C BANK4_LOW
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PP12: WNT 2
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JP14: BK_C BANK4_HIGH
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PP14: WNT 2
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JP16: BK_C BANK5_LOW
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PP16: WNT 2
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Slot12: WT 1
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WNT 1
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Slot13: WT 1
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WNT 1
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Slot14: WT 1
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WNT 1
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Slot15: WT 1
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WNT 1
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Slot16: WT 1
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WNT 1
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Slot17: WT 1
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WNT 1
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U_INT2
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JP18: BK_C BANK5_HIGH
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PP18: WNT 2
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JP20: BK_C BANK6_LOW
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PP20: WNT 2
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JP22: BK_C BANK6_HIGH
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PP22: WNT 2
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Slot18: WT 1
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WNT 1
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Slot19: WT 1
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WNT 1
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Slot20: WT 1
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WNT 1
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Slot21: WT 1
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WNT 1
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Slot22: WT 1
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WNT 1
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Slot23: WT 1
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WNT 1
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U_INT3
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BR SlotTable
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@ -117,24 +141,19 @@ PP22: WNT 2
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;-------------------------------------------------------------------------------
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; Receive a P00 packet
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;
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RX_P00: JMP RFInit ; Init radio
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JMP Receive ; Receive S- and beginning of A-field |
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B_BRFU SD_B_FIELD_OFF ; Receive unprotected full-slot B-field | p: 95 A: 63
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RX_P00: JMP Receive ; Receive S- and beginning of A-field |
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RX_P00_End: B_BRFU SD_B_FIELD_OFF ; Receive unprotected full-slot B-field | p: 95 A: 63
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JMP ReceiveEnd ; End reception | p: 96 B: 0
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BR WriteBMC1 ;
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RX_P00_Sync: JMP RFInit ; Init radio
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JMP ReceiveSync ; Receive S- and beginning of A-field |
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B_BRFU SD_B_FIELD_OFF ; Receive unprotected full-slot B-field | p: 95 A: 63
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JMP ReceiveEnd ; End reception | p: 96 B: 0
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BR WriteBMC1 ;
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RX_P00_Sync: JMP ReceiveSync ; Receive S- and beginning of A-field |
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BR RX_P00_End
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; Receive a P32 packet using the the unprotected full slot B-field format in
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; the D32-field
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;
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RX_P32U_Enc: JMP LoadEncKey
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RX_P32U: JMP RFInit
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JMP Receive
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RX_P32U: JMP Receive
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B_BRFU SD_B_FIELD_OFF ; Receive unprotected full-slot B-field | p: 95 A: 63
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JMP RX_P32U_BZ ; Receive B-field | p: 96 B: 0
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BR WriteBMC2
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@ -142,8 +161,7 @@ RX_P32U: JMP RFInit
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; Receive a P32 packet using the protected full slot B-field format in the
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; D32-field
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;
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RX_P32P: JMP RFInit
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JMP Receive
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RX_P32P: JMP Receive
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B_BRFP SD_B_FIELD_OFF ; Receive protected full slot B-field data | p: 95 A: 63
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JMP TransferP32P_B ; Receive the B-subfields | p: 96-411 B: 0-315
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WT 3 ; | p: 412-414 B: 316-318
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@ -158,8 +176,7 @@ RX_P32P: JMP RFInit
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;-------------------------------------------------------------------------------
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; Transmit a P00 packet
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;
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TX_P00: JMP RFInit ; Init radio
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JMP Transmit ; Transmit S- and beginning of A-field |
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TX_P00: JMP Transmit ; Transmit S- and beginning of A-field |
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JMP TransmitEnd ; End transmission | p: 94 A: 62
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BR label_53 ;
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@ -167,8 +184,7 @@ TX_P00: JMP RFInit ; Init radio
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; D32-field
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;
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TX_P32U_Enc: JMP LoadEncKey
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TX_P32U: JMP RFInit ; Init radio
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JMP Transmit ; Transmit S- and beginning of A-field |
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TX_P32U: JMP Transmit ; Transmit S- and beginning of A-field |
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B_BTFU SD_B_FIELD_OFF ; Transmit unprotected full-slot B-field data | p: 95 A: 63
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JMP TX_P32U_BZ ; Transmit the B- and Z-fields | p: 96 B: 0
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BR label_54 ;
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@ -176,8 +192,7 @@ TX_P32U: JMP RFInit ; Init radio
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; Transmit a P32 packet using the protected full slot B-field format in the
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; D32-field
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;
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TX_P32P: JMP RFInit ; Enable radio
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JMP Transmit ; Transmit S- and beginning of A-field |
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TX_P32P: JMP Transmit ; Transmit S- and beginning of A-field |
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B_BTFP SD_B_FIELD_OFF ; Transmit protect fulls-slot B-field data | p: 95 A: 63
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JMP TransferP32P_B ; Transmit the B-subfields | p: 96-411 B: 0-315
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WT 3 ; | p: 412-414 B: 316-318
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@ -334,14 +349,13 @@ RFInit: RFEN ; Enable RF-clock
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WT U2785_CFG2_LEN + 1
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M_RST
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MEN1
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WT 1
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;WT 1
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P_LDL 0x20
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WT 10
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MEN2
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WT 182
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MEN2N
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P_LDH 0x00
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WT 16
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RTN
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;--------------------------------------------------------------
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@ -393,7 +407,7 @@ SyncLock: JMP RX_P00
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SyncLoop: BR Sync
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;-------------------------------------------------------------
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InitDIP: B_RST
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InitDIP: ;B_RST
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BK_C BANK0_LOW
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C_LD DIP_CC_INIT
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WT 10
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@ -414,10 +428,11 @@ RFStart: BR SyncInit
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SHARED SD_RSSI_OFF,SD_CSUM_OFF,SD_PREAMBLE_OFF,SD_DATA_OFF
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SHARED SlotTable
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SHARED PP0,PP2,PP4,PP6,PP8,PP10,PP12,PP14,PP16,PP18,PP20,PP22
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SHARED JP0,JP2,JP4,JP6,JP8,JP10,JP12,JP14,JP16,JP18,JP20,JP22
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SHARED Slot00,Slot01,Slot02,Slot03,Slot04,Slot05,Slot06,Slot07
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SHARED Slot08,Slot09,Slot10,Slot11,Slot12,Slot13,Slot14,Slot15
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SHARED Slot16,Slot17,Slot18,Slot19,Slot20,Slot21,Slot22,Slot23
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SHARED RFStart,SlotTable
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SHARED RFStart,RFInit
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SHARED SyncInit,Sync,SyncLock,SyncLoop
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SHARED ClockSyncOn,ClockSyncOff,ClockAdjust
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SHARED PSC_ARPD1,PSC_S_SYNC,PSC_S_SYNC_ON,PSC_EOPSM
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@ -7,67 +7,67 @@
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#include "sc1442x_firmware.h"
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const unsigned char sc1442x_firmware[] = {
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0x01, 0x01, 0x01, 0xe4, 0x0d, 0x00, 0x0f, 0x20,
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0x08, 0x02, 0x0f, 0x30, 0x08, 0x02, 0x0f, 0x40,
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0x08, 0x02, 0x61, 0x00, 0x0f, 0x50, 0x08, 0x02,
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0x0f, 0x60, 0x08, 0x02, 0x0f, 0x70, 0x08, 0x02,
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0x6b, 0x00, 0x0f, 0x80, 0x08, 0x02, 0x0f, 0x90,
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0x08, 0x02, 0x0f, 0xa0, 0x08, 0x02, 0x6d, 0x00,
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0x0f, 0xb0, 0x08, 0x02, 0x0f, 0xc0, 0x08, 0x02,
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0x0f, 0xd0, 0x08, 0x02, 0x6f, 0x00, 0x01, 0x02,
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0x02, 0xa8, 0x02, 0x5b, 0x2d, 0x0e, 0x02, 0x85,
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0x01, 0x4f, 0x02, 0xa8, 0x02, 0x6f, 0x2d, 0x0e,
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0x02, 0x85, 0x01, 0x4f, 0x02, 0xbd, 0x02, 0xa8,
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0x02, 0x5b, 0x2d, 0x0e, 0x02, 0x83, 0x01, 0x56,
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0x02, 0xa8, 0x02, 0x5b, 0x3d, 0x0e, 0x02, 0xa0,
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0x09, 0x03, 0x2b, 0x00, 0x09, 0x06, 0x02, 0x85,
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0x39, 0x00, 0x09, 0x06, 0x01, 0x58, 0x02, 0xa8,
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0x02, 0x88, 0x02, 0x97, 0x01, 0x51, 0x02, 0xbd,
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0x02, 0xa8, 0x02, 0x88, 0x25, 0x0e, 0x02, 0x94,
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0x01, 0x52, 0x02, 0xa8, 0x02, 0x88, 0x35, 0x0e,
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0x02, 0xa0, 0x09, 0x03, 0x24, 0x00, 0x09, 0x0d,
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0x20, 0x00, 0x02, 0x97, 0x01, 0x58, 0x39, 0x00,
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0x09, 0x06, 0x20, 0x00, 0xec, 0x50, 0x09, 0x05,
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0x08, 0x01, 0x04, 0x00, 0x39, 0x00, 0x09, 0x06,
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0x20, 0x00, 0xec, 0x50, 0x04, 0x00, 0x20, 0x00,
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0x33, 0x48, 0xed, 0x40, 0xec, 0x01, 0x09, 0x19,
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0x01, 0x01, 0x01, 0xf3, 0x0d, 0x00, 0x09, 0x01,
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0x08, 0x01, 0x09, 0x01, 0x08, 0x01, 0x09, 0x01,
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0x08, 0x01, 0x09, 0x01, 0x08, 0x01, 0x09, 0x01,
|
||||
0x08, 0x01, 0x09, 0x01, 0x08, 0x01, 0x61, 0x00,
|
||||
0x09, 0x01, 0x08, 0x01, 0x09, 0x01, 0x08, 0x01,
|
||||
0x09, 0x01, 0x08, 0x01, 0x09, 0x01, 0x08, 0x01,
|
||||
0x09, 0x01, 0x08, 0x01, 0x09, 0x01, 0x08, 0x01,
|
||||
0x6b, 0x00, 0x09, 0x01, 0x08, 0x01, 0x09, 0x01,
|
||||
0x08, 0x01, 0x09, 0x01, 0x08, 0x01, 0x09, 0x01,
|
||||
0x08, 0x01, 0x09, 0x01, 0x08, 0x01, 0x09, 0x01,
|
||||
0x08, 0x01, 0x6d, 0x00, 0x09, 0x01, 0x08, 0x01,
|
||||
0x09, 0x01, 0x08, 0x01, 0x09, 0x01, 0x08, 0x01,
|
||||
0x09, 0x01, 0x08, 0x01, 0x09, 0x01, 0x08, 0x01,
|
||||
0x09, 0x01, 0x08, 0x01, 0x6f, 0x00, 0x01, 0x02,
|
||||
0x02, 0x6a, 0x2d, 0x0e, 0x02, 0x96, 0x01, 0x5e,
|
||||
0x02, 0x7f, 0x01, 0x39, 0x02, 0xcc, 0x02, 0x6a,
|
||||
0x2d, 0x0e, 0x02, 0x94, 0x01, 0x65, 0x02, 0x6a,
|
||||
0x3d, 0x0e, 0x02, 0xb1, 0x09, 0x03, 0x2b, 0x00,
|
||||
0x09, 0x06, 0x02, 0x96, 0x39, 0x00, 0x09, 0x06,
|
||||
0x01, 0x67, 0x02, 0x99, 0x02, 0xa8, 0x01, 0x60,
|
||||
0x02, 0xcc, 0x02, 0x99, 0x25, 0x0e, 0x02, 0xa5,
|
||||
0x01, 0x61, 0x02, 0x99, 0x35, 0x0e, 0x02, 0xb1,
|
||||
0x09, 0x03, 0x24, 0x00, 0x09, 0x0d, 0x20, 0x00,
|
||||
0x02, 0xa8, 0x01, 0x67, 0x39, 0x00, 0x09, 0x06,
|
||||
0x20, 0x00, 0xec, 0x50, 0x09, 0x05, 0x08, 0x01,
|
||||
0x04, 0x00, 0x39, 0x00, 0x09, 0x06, 0x20, 0x00,
|
||||
0xec, 0x50, 0x04, 0x00, 0x20, 0x00, 0x33, 0x48,
|
||||
0x09, 0x08, 0xed, 0x40, 0xec, 0x01, 0x09, 0x19,
|
||||
0x08, 0x01, 0x09, 0x08, 0x27, 0x00, 0xea, 0x20,
|
||||
0xed, 0x02, 0x09, 0x05, 0x29, 0x00, 0x2c, 0x00,
|
||||
0x09, 0x0c, 0xec, 0x02, 0x09, 0x20, 0xea, 0x00,
|
||||
0x3f, 0x06, 0x09, 0x3e, 0x04, 0x00, 0x20, 0x00,
|
||||
0x33, 0x48, 0xed, 0x40, 0xec, 0x01, 0x09, 0x19,
|
||||
0x08, 0x01, 0x09, 0x08, 0x27, 0x00, 0xea, 0x20,
|
||||
0xed, 0x02, 0x09, 0x05, 0x29, 0x00, 0x2c, 0x00,
|
||||
0x09, 0x0c, 0xec, 0x02, 0x09, 0x20, 0xea, 0x00,
|
||||
0x3f, 0x06, 0x09, 0x3e, 0x04, 0x00, 0x09, 0xf9,
|
||||
0x09, 0x4f, 0xed, 0x01, 0xec, 0x40, 0x01, 0xc5,
|
||||
0xed, 0x00, 0x09, 0x28, 0x20, 0x00, 0x33, 0x40,
|
||||
0x08, 0x01, 0x31, 0x00, 0x09, 0x01, 0xed, 0x10,
|
||||
0x09, 0x25, 0x37, 0x06, 0x09, 0x3e, 0x04, 0x00,
|
||||
0x09, 0xf9, 0x09, 0x54, 0x20, 0x00, 0xec, 0x10,
|
||||
0x09, 0x08, 0xec, 0x00, 0x01, 0xc5, 0x27, 0x00,
|
||||
0x09, 0x0f, 0x26, 0x00, 0x09, 0x3d, 0x04, 0x00,
|
||||
0x09, 0x3d, 0x02, 0x9b, 0x02, 0x9b, 0x02, 0x9b,
|
||||
0x09, 0x01, 0x27, 0x00, 0x09, 0x0b, 0x04, 0x00,
|
||||
0x0b, 0x00, 0x09, 0x02, 0xa4, 0x00, 0xb9, 0x3a,
|
||||
0x09, 0x19, 0xa9, 0x00, 0xa5, 0x00, 0xa4, 0x00,
|
||||
0xb9, 0x3d, 0x09, 0x0a, 0xa9, 0x00, 0xa5, 0x00,
|
||||
0x09, 0x01, 0xec, 0x20, 0x09, 0x0a, 0xa7, 0x00,
|
||||
0x09, 0xb6, 0xa6, 0x00, 0xed, 0x00, 0x09, 0x10,
|
||||
0x04, 0x00, 0x40, 0x00, 0x50, 0x50, 0x09, 0x10,
|
||||
0x50, 0x00, 0x44, 0x00, 0x09, 0x27, 0x44, 0x00,
|
||||
0x04, 0x00, 0x5f, 0x70, 0x09, 0x0b, 0x5f, 0x00,
|
||||
0x40, 0x00, 0x04, 0x00, 0x40, 0x00, 0x57, 0x70,
|
||||
0x09, 0x0b, 0x57, 0x00, 0x04, 0x00, 0x0f, 0x20,
|
||||
0x02, 0xa8, 0x09, 0xfa, 0xea, 0x20, 0xed, 0x42,
|
||||
0x28, 0x00, 0x09, 0x40, 0x26, 0x00, 0x29, 0x00,
|
||||
0x08, 0x14, 0x03, 0xde, 0x20, 0x00, 0x6b, 0x00,
|
||||
0x08, 0x17, 0x01, 0xd0, 0x08, 0x17, 0xea, 0x00,
|
||||
0x02, 0x20, 0x61, 0x00, 0x08, 0x16, 0x01, 0xd0,
|
||||
0x20, 0x00, 0x0f, 0x00, 0xfa, 0x10, 0x09, 0x0a,
|
||||
0x33, 0x00, 0x09, 0x08, 0x20, 0x00, 0x09, 0x0a,
|
||||
0xe9, 0x00, 0xe8, 0x04, 0x62, 0x00, 0x0b, 0x00,
|
||||
0x01, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff};
|
||||
0x33, 0x48, 0x09, 0x08, 0xed, 0x40, 0xec, 0x01,
|
||||
0x09, 0x19, 0x08, 0x01, 0x09, 0x08, 0x27, 0x00,
|
||||
0xea, 0x20, 0xed, 0x02, 0x09, 0x05, 0x29, 0x00,
|
||||
0x2c, 0x00, 0x09, 0x0c, 0xec, 0x02, 0x09, 0x20,
|
||||
0xea, 0x00, 0x3f, 0x06, 0x09, 0x3e, 0x04, 0x00,
|
||||
0x09, 0xf9, 0x09, 0x4f, 0xed, 0x01, 0xec, 0x40,
|
||||
0x01, 0xd4, 0xed, 0x00, 0x09, 0x28, 0x20, 0x00,
|
||||
0x33, 0x40, 0x08, 0x01, 0x31, 0x00, 0x09, 0x01,
|
||||
0xed, 0x10, 0x09, 0x25, 0x37, 0x06, 0x09, 0x3e,
|
||||
0x04, 0x00, 0x09, 0xf9, 0x09, 0x54, 0x20, 0x00,
|
||||
0xec, 0x10, 0x09, 0x08, 0xec, 0x00, 0x01, 0xd4,
|
||||
0x27, 0x00, 0x09, 0x0f, 0x26, 0x00, 0x09, 0x3d,
|
||||
0x04, 0x00, 0x09, 0x3d, 0x02, 0xac, 0x02, 0xac,
|
||||
0x02, 0xac, 0x09, 0x01, 0x27, 0x00, 0x09, 0x0b,
|
||||
0x04, 0x00, 0x0b, 0x00, 0x09, 0x02, 0xa4, 0x00,
|
||||
0xb9, 0x3a, 0x09, 0x19, 0xa9, 0x00, 0xa5, 0x00,
|
||||
0xa4, 0x00, 0xb9, 0x3d, 0x09, 0x0a, 0xa9, 0x00,
|
||||
0xa5, 0x00, 0xec, 0x20, 0x09, 0x0a, 0xa7, 0x00,
|
||||
0x09, 0xb6, 0xa6, 0x00, 0x09, 0x10, 0x04, 0x00,
|
||||
0x40, 0x00, 0x50, 0x50, 0x09, 0x10, 0x50, 0x00,
|
||||
0x44, 0x00, 0x09, 0x27, 0x44, 0x00, 0x04, 0x00,
|
||||
0x5f, 0x70, 0x09, 0x0b, 0x5f, 0x00, 0x40, 0x00,
|
||||
0x04, 0x00, 0x40, 0x00, 0x57, 0x70, 0x09, 0x0b,
|
||||
0x57, 0x00, 0x04, 0x00, 0x0f, 0x20, 0x02, 0xb9,
|
||||
0x09, 0xfa, 0xea, 0x20, 0xed, 0x42, 0x28, 0x00,
|
||||
0x09, 0x40, 0x26, 0x00, 0x29, 0x00, 0x08, 0x14,
|
||||
0x03, 0xed, 0x20, 0x00, 0x6b, 0x00, 0x08, 0x17,
|
||||
0x01, 0xdf, 0x08, 0x17, 0xea, 0x00, 0x02, 0x38,
|
||||
0x61, 0x00, 0x08, 0x16, 0x01, 0xdf, 0x0f, 0x00,
|
||||
0xfa, 0x10, 0x09, 0x0a, 0x33, 0x00, 0x09, 0x08,
|
||||
0x20, 0x00, 0x09, 0x0a, 0xe9, 0x00, 0xe8, 0x04,
|
||||
0x62, 0x00, 0x0b, 0x00, 0x01, 0xde};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#ifndef SC1442X_FIRMWARE
|
||||
#define SC1442X_FIRMWARE
|
||||
|
||||
extern const unsigned char sc1442x_firmware[509];
|
||||
extern const unsigned char sc1442x_firmware[510];
|
||||
|
||||
#define DIP_CC_INIT 0x10
|
||||
#define RF_DESC 0x3A
|
||||
|
|
@ -14,57 +14,57 @@ extern const unsigned char sc1442x_firmware[509];
|
|||
#define SD_PREAMBLE_OFF 0x1
|
||||
#define SD_DATA_OFF 0x6
|
||||
#define SlotTable 0x2
|
||||
#define PP0 0x4
|
||||
#define PP2 0x6
|
||||
#define PP4 0x8
|
||||
#define PP6 0xB
|
||||
#define PP8 0xD
|
||||
#define PP10 0xF
|
||||
#define PP12 0x12
|
||||
#define PP14 0x14
|
||||
#define PP16 0x16
|
||||
#define PP18 0x19
|
||||
#define PP20 0x1B
|
||||
#define PP22 0x1D
|
||||
#define JP0 0x3
|
||||
#define JP2 0x5
|
||||
#define JP4 0x7
|
||||
#define JP6 0xA
|
||||
#define JP8 0xC
|
||||
#define JP10 0xE
|
||||
#define JP12 0x11
|
||||
#define JP14 0x13
|
||||
#define JP16 0x15
|
||||
#define JP18 0x18
|
||||
#define JP20 0x1A
|
||||
#define JP22 0x1C
|
||||
#define RFStart 0xF0
|
||||
#define SlotTable 0x2
|
||||
#define SyncInit 0xCF
|
||||
#define Sync 0xD0
|
||||
#define SyncLock 0xE0
|
||||
#define SyncLoop 0xE3
|
||||
#define ClockSyncOn 0x63
|
||||
#define ClockSyncOff 0x6B
|
||||
#define ClockAdjust 0x67
|
||||
#define Slot00 0x3
|
||||
#define Slot01 0x5
|
||||
#define Slot02 0x7
|
||||
#define Slot03 0x9
|
||||
#define Slot04 0xB
|
||||
#define Slot05 0xD
|
||||
#define Slot06 0x10
|
||||
#define Slot07 0x12
|
||||
#define Slot08 0x14
|
||||
#define Slot09 0x16
|
||||
#define Slot10 0x18
|
||||
#define Slot11 0x1A
|
||||
#define Slot12 0x1D
|
||||
#define Slot13 0x1F
|
||||
#define Slot14 0x21
|
||||
#define Slot15 0x23
|
||||
#define Slot16 0x25
|
||||
#define Slot17 0x27
|
||||
#define Slot18 0x2A
|
||||
#define Slot19 0x2C
|
||||
#define Slot20 0x2E
|
||||
#define Slot21 0x30
|
||||
#define Slot22 0x32
|
||||
#define Slot23 0x34
|
||||
#define RFStart 0xFE
|
||||
#define RFInit 0xB9
|
||||
#define SyncInit 0xDE
|
||||
#define Sync 0xDF
|
||||
#define SyncLock 0xEF
|
||||
#define SyncLoop 0xF2
|
||||
#define ClockSyncOn 0x73
|
||||
#define ClockSyncOff 0x7B
|
||||
#define ClockAdjust 0x77
|
||||
#define PSC_ARPD1 0x80
|
||||
#define PSC_S_SYNC 0x40
|
||||
#define PSC_S_SYNC_ON 0x20
|
||||
#define PSC_EOPSM 0x10
|
||||
#define RX_P00 0x20
|
||||
#define RX_P00_Sync 0x25
|
||||
#define RX_P32U 0x2B
|
||||
#define RX_P32P 0x30
|
||||
#define RX_P32U_Enc 0x2A
|
||||
#define TX_P00 0x3B
|
||||
#define TX_P32U 0x40
|
||||
#define TX_P32P 0x45
|
||||
#define TX_P32U_Enc 0x3F
|
||||
#define RX_P00 0x38
|
||||
#define RX_P00_Sync 0x3C
|
||||
#define RX_P32U 0x3F
|
||||
#define RX_P32P 0x43
|
||||
#define RX_P32U_Enc 0x3E
|
||||
#define TX_P00 0x4D
|
||||
#define TX_P32U 0x51
|
||||
#define TX_P32P 0x55
|
||||
#define TX_P32U_Enc 0x50
|
||||
#define DCS_IV 0x50
|
||||
#define DCS_CK 0x58
|
||||
#define DCS_STATE 0x70
|
||||
#define DCS_STATE_SIZE 0xB
|
||||
#define LoadEncKey 0xBD
|
||||
#define LoadEncState 0xCA
|
||||
#define LoadEncKey 0xCC
|
||||
#define LoadEncState 0xD9
|
||||
|
||||
#endif /* SC1442X_FIRMWARE */
|
||||
|
|
|
|||
Reference in New Issue