2007-04-27 01:53:52 +00:00
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#ifndef _ASM_POWERPC_MMU_HASH64_H_
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#define _ASM_POWERPC_MMU_HASH64_H_
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/*
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* PowerPC64 memory management structures
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*
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* Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
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* PPC64 rework.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/asm-compat.h>
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#include <asm/page.h>
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2012-09-10 02:52:57 +00:00
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/*
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* This is necessary to get the definition of PGTABLE_RANGE which we
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* need for various slices related matters. Note that this isn't the
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* complete pgtable.h but only a portion of it.
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*/
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#include <asm/pgtable-ppc64.h>
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2007-04-27 01:53:52 +00:00
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/*
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* Segment table
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*/
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#define STE_ESID_V 0x80
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#define STE_ESID_KS 0x20
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#define STE_ESID_KP 0x10
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#define STE_ESID_N 0x08
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#define STE_VSID_SHIFT 12
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/* Location of cpu0's segment table */
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2011-03-06 18:09:07 +00:00
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#define STAB0_PAGE 0x8
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2007-04-27 01:53:52 +00:00
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#define STAB0_OFFSET (STAB0_PAGE << 12)
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#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
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#ifndef __ASSEMBLY__
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extern char initial_stab[];
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#endif /* ! __ASSEMBLY */
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/*
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* SLB
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*/
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#define SLB_NUM_BOLTED 3
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#define SLB_CACHE_ENTRIES 8
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2009-08-28 12:06:29 +00:00
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#define SLB_MIN_SIZE 32
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2007-04-27 01:53:52 +00:00
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/* Bits in the SLB ESID word */
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#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
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/* Bits in the SLB VSID word */
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#define SLB_VSID_SHIFT 12
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2007-10-11 10:37:10 +00:00
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#define SLB_VSID_SHIFT_1T 24
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#define SLB_VSID_SSIZE_SHIFT 62
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2007-04-27 01:53:52 +00:00
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#define SLB_VSID_B ASM_CONST(0xc000000000000000)
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#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
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#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
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#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
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#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
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#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
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#define SLB_VSID_L ASM_CONST(0x0000000000000100)
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#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
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#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
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#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
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#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
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#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
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#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
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#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
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#define SLB_VSID_KERNEL (SLB_VSID_KP)
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#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
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#define SLBIE_C (0x08000000)
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2007-10-11 10:37:10 +00:00
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#define SLBIE_SSIZE_SHIFT 25
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2007-04-27 01:53:52 +00:00
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/*
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* Hash table
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*/
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#define HPTES_PER_GROUP 8
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2007-05-10 05:28:44 +00:00
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#define HPTE_V_SSIZE_SHIFT 62
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2007-04-27 01:53:52 +00:00
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#define HPTE_V_AVPN_SHIFT 7
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2007-05-10 05:28:44 +00:00
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#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
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2007-04-27 01:53:52 +00:00
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#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
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2007-11-26 16:24:43 +00:00
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#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
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2007-04-27 01:53:52 +00:00
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#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
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#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
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#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
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#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
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#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
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#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
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#define HPTE_R_TS ASM_CONST(0x4000000000000000)
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KVM: PPC: Add support for Book3S processors in hypervisor mode
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged instructions and access privileged
registers itself without trapping to the host. This gives excellent
performance, but does mean that KVM cannot emulate a processor
architecture other than the one that the hardware implements.
This code assumes that the guest is running paravirtualized using the
PAPR (Power Architecture Platform Requirements) interface, which is the
interface that IBM's PowerVM hypervisor uses. That means that existing
Linux distributions that run on IBM pSeries machines will also run
under KVM without modification. In order to communicate the PAPR
hypercalls to qemu, this adds a new KVM_EXIT_PAPR_HCALL exit code
to include/linux/kvm.h.
Currently the choice between book3s_hv support and book3s_pr support
(i.e. the existing code, which runs the guest in user mode) has to be
made at kernel configuration time, so a given kernel binary can only
do one or the other.
This new book3s_hv code doesn't support MMIO emulation at present.
Since we are running paravirtualized guests, this isn't a serious
restriction.
With the guest running in supervisor mode, most exceptions go straight
to the guest. We will never get data or instruction storage or segment
interrupts, alignment interrupts, decrementer interrupts, program
interrupts, single-step interrupts, etc., coming to the hypervisor from
the guest. Therefore this introduces a new KVMTEST_NONHV macro for the
exception entry path so that we don't have to do the KVM test on entry
to those exception handlers.
We do however get hypervisor decrementer, hypervisor data storage,
hypervisor instruction storage, and hypervisor emulation assist
interrupts, so we have to handle those.
In hypervisor mode, real-mode accesses can access all of RAM, not just
a limited amount. Therefore we put all the guest state in the vcpu.arch
and use the shadow_vcpu in the PACA only for temporary scratch space.
We allocate the vcpu with kzalloc rather than vzalloc, and we don't use
anything in the kvmppc_vcpu_book3s struct, so we don't allocate it.
We don't have a shared page with the guest, but we still need a
kvm_vcpu_arch_shared struct to store the values of various registers,
so we include one in the vcpu_arch struct.
The POWER7 processor has a restriction that all threads in a core have
to be in the same partition. MMU-on kernel code counts as a partition
(partition 0), so we have to do a partition switch on every entry to and
exit from the guest. At present we require the host and guest to run
in single-thread mode because of this hardware restriction.
This code allocates a hashed page table for the guest and initializes
it with HPTEs for the guest's Virtual Real Memory Area (VRMA). We
require that the guest memory is allocated using 16MB huge pages, in
order to simplify the low-level memory management. This also means that
we can get away without tracking paging activity in the host for now,
since huge pages can't be paged or swapped.
This also adds a few new exports needed by the book3s_hv code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:21:34 +00:00
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#define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
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2007-04-27 01:53:52 +00:00
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#define HPTE_R_RPN_SHIFT 12
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KVM: PPC: Add support for Book3S processors in hypervisor mode
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged instructions and access privileged
registers itself without trapping to the host. This gives excellent
performance, but does mean that KVM cannot emulate a processor
architecture other than the one that the hardware implements.
This code assumes that the guest is running paravirtualized using the
PAPR (Power Architecture Platform Requirements) interface, which is the
interface that IBM's PowerVM hypervisor uses. That means that existing
Linux distributions that run on IBM pSeries machines will also run
under KVM without modification. In order to communicate the PAPR
hypercalls to qemu, this adds a new KVM_EXIT_PAPR_HCALL exit code
to include/linux/kvm.h.
Currently the choice between book3s_hv support and book3s_pr support
(i.e. the existing code, which runs the guest in user mode) has to be
made at kernel configuration time, so a given kernel binary can only
do one or the other.
This new book3s_hv code doesn't support MMIO emulation at present.
Since we are running paravirtualized guests, this isn't a serious
restriction.
With the guest running in supervisor mode, most exceptions go straight
to the guest. We will never get data or instruction storage or segment
interrupts, alignment interrupts, decrementer interrupts, program
interrupts, single-step interrupts, etc., coming to the hypervisor from
the guest. Therefore this introduces a new KVMTEST_NONHV macro for the
exception entry path so that we don't have to do the KVM test on entry
to those exception handlers.
We do however get hypervisor decrementer, hypervisor data storage,
hypervisor instruction storage, and hypervisor emulation assist
interrupts, so we have to handle those.
In hypervisor mode, real-mode accesses can access all of RAM, not just
a limited amount. Therefore we put all the guest state in the vcpu.arch
and use the shadow_vcpu in the PACA only for temporary scratch space.
We allocate the vcpu with kzalloc rather than vzalloc, and we don't use
anything in the kvmppc_vcpu_book3s struct, so we don't allocate it.
We don't have a shared page with the guest, but we still need a
kvm_vcpu_arch_shared struct to store the values of various registers,
so we include one in the vcpu_arch struct.
The POWER7 processor has a restriction that all threads in a core have
to be in the same partition. MMU-on kernel code counts as a partition
(partition 0), so we have to do a partition switch on every entry to and
exit from the guest. At present we require the host and guest to run
in single-thread mode because of this hardware restriction.
This code allocates a hashed page table for the guest and initializes
it with HPTEs for the guest's Virtual Real Memory Area (VRMA). We
require that the guest memory is allocated using 16MB huge pages, in
order to simplify the low-level memory management. This also means that
we can get away without tracking paging activity in the host for now,
since huge pages can't be paged or swapped.
This also adds a few new exports needed by the book3s_hv code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:21:34 +00:00
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#define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
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2007-04-27 01:53:52 +00:00
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#define HPTE_R_PP ASM_CONST(0x0000000000000003)
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#define HPTE_R_N ASM_CONST(0x0000000000000004)
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KVM: PPC: Add support for Book3S processors in hypervisor mode
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged instructions and access privileged
registers itself without trapping to the host. This gives excellent
performance, but does mean that KVM cannot emulate a processor
architecture other than the one that the hardware implements.
This code assumes that the guest is running paravirtualized using the
PAPR (Power Architecture Platform Requirements) interface, which is the
interface that IBM's PowerVM hypervisor uses. That means that existing
Linux distributions that run on IBM pSeries machines will also run
under KVM without modification. In order to communicate the PAPR
hypercalls to qemu, this adds a new KVM_EXIT_PAPR_HCALL exit code
to include/linux/kvm.h.
Currently the choice between book3s_hv support and book3s_pr support
(i.e. the existing code, which runs the guest in user mode) has to be
made at kernel configuration time, so a given kernel binary can only
do one or the other.
This new book3s_hv code doesn't support MMIO emulation at present.
Since we are running paravirtualized guests, this isn't a serious
restriction.
With the guest running in supervisor mode, most exceptions go straight
to the guest. We will never get data or instruction storage or segment
interrupts, alignment interrupts, decrementer interrupts, program
interrupts, single-step interrupts, etc., coming to the hypervisor from
the guest. Therefore this introduces a new KVMTEST_NONHV macro for the
exception entry path so that we don't have to do the KVM test on entry
to those exception handlers.
We do however get hypervisor decrementer, hypervisor data storage,
hypervisor instruction storage, and hypervisor emulation assist
interrupts, so we have to handle those.
In hypervisor mode, real-mode accesses can access all of RAM, not just
a limited amount. Therefore we put all the guest state in the vcpu.arch
and use the shadow_vcpu in the PACA only for temporary scratch space.
We allocate the vcpu with kzalloc rather than vzalloc, and we don't use
anything in the kvmppc_vcpu_book3s struct, so we don't allocate it.
We don't have a shared page with the guest, but we still need a
kvm_vcpu_arch_shared struct to store the values of various registers,
so we include one in the vcpu_arch struct.
The POWER7 processor has a restriction that all threads in a core have
to be in the same partition. MMU-on kernel code counts as a partition
(partition 0), so we have to do a partition switch on every entry to and
exit from the guest. At present we require the host and guest to run
in single-thread mode because of this hardware restriction.
This code allocates a hashed page table for the guest and initializes
it with HPTEs for the guest's Virtual Real Memory Area (VRMA). We
require that the guest memory is allocated using 16MB huge pages, in
order to simplify the low-level memory management. This also means that
we can get away without tracking paging activity in the host for now,
since huge pages can't be paged or swapped.
This also adds a few new exports needed by the book3s_hv code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:21:34 +00:00
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#define HPTE_R_G ASM_CONST(0x0000000000000008)
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#define HPTE_R_M ASM_CONST(0x0000000000000010)
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#define HPTE_R_I ASM_CONST(0x0000000000000020)
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#define HPTE_R_W ASM_CONST(0x0000000000000040)
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#define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
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2007-04-27 01:53:52 +00:00
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#define HPTE_R_C ASM_CONST(0x0000000000000080)
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#define HPTE_R_R ASM_CONST(0x0000000000000100)
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KVM: PPC: Add support for Book3S processors in hypervisor mode
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged instructions and access privileged
registers itself without trapping to the host. This gives excellent
performance, but does mean that KVM cannot emulate a processor
architecture other than the one that the hardware implements.
This code assumes that the guest is running paravirtualized using the
PAPR (Power Architecture Platform Requirements) interface, which is the
interface that IBM's PowerVM hypervisor uses. That means that existing
Linux distributions that run on IBM pSeries machines will also run
under KVM without modification. In order to communicate the PAPR
hypercalls to qemu, this adds a new KVM_EXIT_PAPR_HCALL exit code
to include/linux/kvm.h.
Currently the choice between book3s_hv support and book3s_pr support
(i.e. the existing code, which runs the guest in user mode) has to be
made at kernel configuration time, so a given kernel binary can only
do one or the other.
This new book3s_hv code doesn't support MMIO emulation at present.
Since we are running paravirtualized guests, this isn't a serious
restriction.
With the guest running in supervisor mode, most exceptions go straight
to the guest. We will never get data or instruction storage or segment
interrupts, alignment interrupts, decrementer interrupts, program
interrupts, single-step interrupts, etc., coming to the hypervisor from
the guest. Therefore this introduces a new KVMTEST_NONHV macro for the
exception entry path so that we don't have to do the KVM test on entry
to those exception handlers.
We do however get hypervisor decrementer, hypervisor data storage,
hypervisor instruction storage, and hypervisor emulation assist
interrupts, so we have to handle those.
In hypervisor mode, real-mode accesses can access all of RAM, not just
a limited amount. Therefore we put all the guest state in the vcpu.arch
and use the shadow_vcpu in the PACA only for temporary scratch space.
We allocate the vcpu with kzalloc rather than vzalloc, and we don't use
anything in the kvmppc_vcpu_book3s struct, so we don't allocate it.
We don't have a shared page with the guest, but we still need a
kvm_vcpu_arch_shared struct to store the values of various registers,
so we include one in the vcpu_arch struct.
The POWER7 processor has a restriction that all threads in a core have
to be in the same partition. MMU-on kernel code counts as a partition
(partition 0), so we have to do a partition switch on every entry to and
exit from the guest. At present we require the host and guest to run
in single-thread mode because of this hardware restriction.
This code allocates a hashed page table for the guest and initializes
it with HPTEs for the guest's Virtual Real Memory Area (VRMA). We
require that the guest memory is allocated using 16MB huge pages, in
order to simplify the low-level memory management. This also means that
we can get away without tracking paging activity in the host for now,
since huge pages can't be paged or swapped.
This also adds a few new exports needed by the book3s_hv code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:21:34 +00:00
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#define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
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2007-04-27 01:53:52 +00:00
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2007-06-14 05:31:34 +00:00
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#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
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#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
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2007-04-27 01:53:52 +00:00
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/* Values for PP (assumes Ks=0, Kp=1) */
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#define PP_RWXX 0 /* Supervisor read/write, User none */
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#define PP_RWRX 1 /* Supervisor read/write, User read */
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#define PP_RWRW 2 /* Supervisor read/write, User read/write */
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#define PP_RXRX 3 /* Supervisor read, User read */
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KVM: PPC: Implement MMIO emulation support for Book3S HV guests
This provides the low-level support for MMIO emulation in Book3S HV
guests. When the guest tries to map a page which is not covered by
any memslot, that page is taken to be an MMIO emulation page. Instead
of inserting a valid HPTE, we insert an HPTE that has the valid bit
clear but another hypervisor software-use bit set, which we call
HPTE_V_ABSENT, to indicate that this is an absent page. An
absent page is treated much like a valid page as far as guest hcalls
(H_ENTER, H_REMOVE, H_READ etc.) are concerned, except of course that
an absent HPTE doesn't need to be invalidated with tlbie since it
was never valid as far as the hardware is concerned.
When the guest accesses a page for which there is an absent HPTE, it
will take a hypervisor data storage interrupt (HDSI) since we now set
the VPM1 bit in the LPCR. Our HDSI handler for HPTE-not-present faults
looks up the hash table and if it finds an absent HPTE mapping the
requested virtual address, will switch to kernel mode and handle the
fault in kvmppc_book3s_hv_page_fault(), which at present just calls
kvmppc_hv_emulate_mmio() to set up the MMIO emulation.
This is based on an earlier patch by Benjamin Herrenschmidt, but since
heavily reworked.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 12:36:37 +00:00
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#define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
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2007-04-27 01:53:52 +00:00
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KVM: PPC: Book3S HV: Handle guest-caused machine checks on POWER7 without panicking
Currently, if a machine check interrupt happens while we are in the
guest, we exit the guest and call the host's machine check handler,
which tends to cause the host to panic. Some machine checks can be
triggered by the guest; for example, if the guest creates two entries
in the SLB that map the same effective address, and then accesses that
effective address, the CPU will take a machine check interrupt.
To handle this better, when a machine check happens inside the guest,
we call a new function, kvmppc_realmode_machine_check(), while still in
real mode before exiting the guest. On POWER7, it handles the cases
that the guest can trigger, either by flushing and reloading the SLB,
or by flushing the TLB, and then it delivers the machine check interrupt
directly to the guest without going back to the host. On POWER7, the
OPAL firmware patches the machine check interrupt vector so that it
gets control first, and it leaves behind its analysis of the situation
in a structure pointed to by the opal_mc_evt field of the paca. The
kvmppc_realmode_machine_check() function looks at this, and if OPAL
reports that there was no error, or that it has handled the error, we
also go straight back to the guest with a machine check. We have to
deliver a machine check to the guest since the machine check interrupt
might have trashed valid values in SRR0/1.
If the machine check is one we can't handle in real mode, and one that
OPAL hasn't already handled, or on PPC970, we exit the guest and call
the host's machine check handler. We do this by jumping to the
machine_check_fwnmi label, rather than absolute address 0x200, because
we don't want to re-execute OPAL's handler on POWER7. On PPC970, the
two are equivalent because address 0x200 just contains a branch.
Then, if the host machine check handler decides that the system can
continue executing, kvmppc_handle_exit() delivers a machine check
interrupt to the guest -- once again to let the guest know that SRR0/1
have been modified.
Signed-off-by: Paul Mackerras <paulus@samba.org>
[agraf: fix checkpatch warnings]
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-23 22:37:50 +00:00
|
|
|
/* Fields for tlbiel instruction in architecture 2.06 */
|
|
|
|
|
#define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */
|
|
|
|
|
#define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */
|
|
|
|
|
#define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */
|
|
|
|
|
#define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */
|
|
|
|
|
#define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */
|
|
|
|
|
#define TLBIEL_INVAL_SET_SHIFT 12
|
|
|
|
|
|
|
|
|
|
#define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
|
|
|
|
|
|
2007-04-27 01:53:52 +00:00
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
|
2007-06-13 04:52:56 +00:00
|
|
|
struct hash_pte {
|
2007-04-27 01:53:52 +00:00
|
|
|
unsigned long v;
|
|
|
|
|
unsigned long r;
|
2007-06-13 04:52:56 +00:00
|
|
|
};
|
2007-04-27 01:53:52 +00:00
|
|
|
|
2007-06-13 04:52:56 +00:00
|
|
|
extern struct hash_pte *htab_address;
|
2007-04-27 01:53:52 +00:00
|
|
|
extern unsigned long htab_size_bytes;
|
|
|
|
|
extern unsigned long htab_hash_mask;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Page size definition
|
|
|
|
|
*
|
|
|
|
|
* shift : is the "PAGE_SHIFT" value for that page size
|
|
|
|
|
* sllp : is a bit mask with the value of SLB L || LP to be or'ed
|
|
|
|
|
* directly to a slbmte "vsid" value
|
|
|
|
|
* penc : is the HPTE encoding mask for the "LP" field:
|
|
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
struct mmu_psize_def
|
|
|
|
|
{
|
|
|
|
|
unsigned int shift; /* number of bits */
|
|
|
|
|
unsigned int penc; /* HPTE encoding */
|
|
|
|
|
unsigned int tlbiel; /* tlbiel supported for that page size */
|
|
|
|
|
unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
|
|
|
|
|
unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
|
2007-05-10 05:28:44 +00:00
|
|
|
/*
|
|
|
|
|
* Segment sizes.
|
|
|
|
|
* These are the values used by hardware in the B field of
|
|
|
|
|
* SLB entries and the first dword of MMU hashtable entries.
|
|
|
|
|
* The B field is 2 bits; the values 2 and 3 are unused and reserved.
|
|
|
|
|
*/
|
|
|
|
|
#define MMU_SEGSIZE_256M 0
|
|
|
|
|
#define MMU_SEGSIZE_1T 1
|
|
|
|
|
|
2012-09-10 02:52:50 +00:00
|
|
|
/*
|
|
|
|
|
* encode page number shift.
|
|
|
|
|
* in order to fit the 78 bit va in a 64 bit variable we shift the va by
|
|
|
|
|
* 12 bits. This enable us to address upto 76 bit va.
|
|
|
|
|
* For hpt hash from a va we can ignore the page size bits of va and for
|
|
|
|
|
* hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
|
|
|
|
|
* we work in all cases including 4k page size.
|
|
|
|
|
*/
|
|
|
|
|
#define VPN_SHIFT 12
|
2007-10-11 10:37:10 +00:00
|
|
|
|
2007-04-27 01:53:52 +00:00
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
|
2012-09-10 02:52:50 +00:00
|
|
|
static inline int segment_shift(int ssize)
|
|
|
|
|
{
|
|
|
|
|
if (ssize == MMU_SEGSIZE_256M)
|
|
|
|
|
return SID_SHIFT;
|
|
|
|
|
return SID_SHIFT_1T;
|
|
|
|
|
}
|
|
|
|
|
|
2007-04-27 01:53:52 +00:00
|
|
|
/*
|
2007-10-11 10:37:10 +00:00
|
|
|
* The current system page and segment sizes
|
2007-04-27 01:53:52 +00:00
|
|
|
*/
|
|
|
|
|
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
|
|
|
|
|
extern int mmu_linear_psize;
|
|
|
|
|
extern int mmu_virtual_psize;
|
|
|
|
|
extern int mmu_vmalloc_psize;
|
[POWERPC] vmemmap fixes to use smaller pages
This changes vmemmap to use a different region (region 0xf) of the
address space, and to configure the page size of that region
dynamically at boot.
The problem with the current approach of always using 16M pages is that
it's not well suited to machines that have small amounts of memory such
as small partitions on pseries, or PS3's.
In fact, on the PS3, failure to allocate the 16M page backing vmmemmap
tends to prevent hotplugging the HV's "additional" memory, thus limiting
the available memory even more, from my experience down to something
like 80M total, which makes it really not very useable.
The logic used by my match to choose the vmemmap page size is:
- If 16M pages are available and there's 1G or more RAM at boot,
use that size.
- Else if 64K pages are available, use that
- Else use 4K pages
I've tested on a POWER6 (16M pages) and on an iSeries POWER3 (4K pages)
and it seems to work fine.
Note that I intend to change the way we organize the kernel regions &
SLBs so the actual region will change from 0xf back to something else at
one point, as I simplify the SLB miss handler, but that will be for a
later patch.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-04-30 05:41:48 +00:00
|
|
|
extern int mmu_vmemmap_psize;
|
2007-04-27 01:53:52 +00:00
|
|
|
extern int mmu_io_psize;
|
2007-10-11 10:37:10 +00:00
|
|
|
extern int mmu_kernel_ssize;
|
|
|
|
|
extern int mmu_highuser_ssize;
|
2007-12-06 06:24:48 +00:00
|
|
|
extern u16 mmu_slb_size;
|
2008-05-08 04:27:08 +00:00
|
|
|
extern unsigned long tce_alloc_start, tce_alloc_end;
|
2007-04-27 01:53:52 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* If the processor supports 64k normal pages but not 64k cache
|
|
|
|
|
* inhibited pages, we have to be prepared to switch processes
|
|
|
|
|
* to use 4k pages when they create cache-inhibited mappings.
|
|
|
|
|
* If this is the case, mmu_ci_restrictions will be set to 1.
|
|
|
|
|
*/
|
|
|
|
|
extern int mmu_ci_restrictions;
|
|
|
|
|
|
2012-09-10 02:52:50 +00:00
|
|
|
/*
|
|
|
|
|
* This computes the AVPN and B fields of the first dword of a HPTE,
|
|
|
|
|
* for use when we want to match an existing PTE. The bottom 7 bits
|
|
|
|
|
* of the returned value are zero.
|
|
|
|
|
*/
|
|
|
|
|
static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
|
|
|
|
|
int ssize)
|
|
|
|
|
{
|
|
|
|
|
unsigned long v;
|
|
|
|
|
/*
|
|
|
|
|
* The AVA field omits the low-order 23 bits of the 78 bits VA.
|
|
|
|
|
* These bits are not needed in the PTE, because the
|
|
|
|
|
* low-order b of these bits are part of the byte offset
|
|
|
|
|
* into the virtual page and, if b < 23, the high-order
|
|
|
|
|
* 23-b of these bits are always used in selecting the
|
|
|
|
|
* PTEGs to be searched
|
|
|
|
|
*/
|
|
|
|
|
v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
|
|
|
|
|
v <<= HPTE_V_AVPN_SHIFT;
|
|
|
|
|
v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
|
|
|
|
|
return v;
|
|
|
|
|
}
|
|
|
|
|
|
2007-04-27 01:53:52 +00:00
|
|
|
/*
|
|
|
|
|
* This function sets the AVPN and L fields of the HPTE appropriately
|
|
|
|
|
* for the page size
|
|
|
|
|
*/
|
2012-09-10 02:52:50 +00:00
|
|
|
static inline unsigned long hpte_encode_v(unsigned long vpn,
|
|
|
|
|
int psize, int ssize)
|
2007-04-27 01:53:52 +00:00
|
|
|
{
|
2007-10-11 10:37:10 +00:00
|
|
|
unsigned long v;
|
2012-09-10 02:52:50 +00:00
|
|
|
v = hpte_encode_avpn(vpn, psize, ssize);
|
2007-04-27 01:53:52 +00:00
|
|
|
if (psize != MMU_PAGE_4K)
|
|
|
|
|
v |= HPTE_V_LARGE;
|
|
|
|
|
return v;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This function sets the ARPN, and LP fields of the HPTE appropriately
|
|
|
|
|
* for the page size. We assume the pa is already "clean" that is properly
|
|
|
|
|
* aligned for the requested page size
|
|
|
|
|
*/
|
|
|
|
|
static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
|
|
|
|
|
{
|
|
|
|
|
unsigned long r;
|
|
|
|
|
|
|
|
|
|
/* A 4K page needs no special encoding */
|
|
|
|
|
if (psize == MMU_PAGE_4K)
|
|
|
|
|
return pa & HPTE_R_RPN;
|
|
|
|
|
else {
|
|
|
|
|
unsigned int penc = mmu_psize_defs[psize].penc;
|
|
|
|
|
unsigned int shift = mmu_psize_defs[psize].shift;
|
|
|
|
|
return (pa & ~((1ul << shift) - 1)) | (penc << 12);
|
|
|
|
|
}
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
2012-09-10 02:52:50 +00:00
|
|
|
* Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
|
2007-04-27 01:53:52 +00:00
|
|
|
*/
|
2012-09-10 02:52:50 +00:00
|
|
|
static inline unsigned long hpt_vpn(unsigned long ea,
|
|
|
|
|
unsigned long vsid, int ssize)
|
2007-10-11 10:37:10 +00:00
|
|
|
{
|
2012-09-10 02:52:50 +00:00
|
|
|
unsigned long mask;
|
|
|
|
|
int s_shift = segment_shift(ssize);
|
|
|
|
|
|
|
|
|
|
mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
|
|
|
|
|
return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
|
2007-10-11 10:37:10 +00:00
|
|
|
}
|
2007-04-27 01:53:52 +00:00
|
|
|
|
2007-10-11 10:37:10 +00:00
|
|
|
/*
|
|
|
|
|
* This hashes a virtual address
|
|
|
|
|
*/
|
2012-09-10 02:52:50 +00:00
|
|
|
static inline unsigned long hpt_hash(unsigned long vpn,
|
|
|
|
|
unsigned int shift, int ssize)
|
2007-04-27 01:53:52 +00:00
|
|
|
{
|
2012-09-10 02:52:50 +00:00
|
|
|
int mask;
|
2007-10-11 10:37:10 +00:00
|
|
|
unsigned long hash, vsid;
|
|
|
|
|
|
2012-09-10 02:52:50 +00:00
|
|
|
/* VPN_SHIFT can be atmost 12 */
|
2007-10-11 10:37:10 +00:00
|
|
|
if (ssize == MMU_SEGSIZE_256M) {
|
2012-09-10 02:52:50 +00:00
|
|
|
mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
|
|
|
|
|
hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
|
|
|
|
|
((vpn & mask) >> (shift - VPN_SHIFT));
|
2007-10-11 10:37:10 +00:00
|
|
|
} else {
|
2012-09-10 02:52:50 +00:00
|
|
|
mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
|
|
|
|
|
vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
|
|
|
|
|
hash = vsid ^ (vsid << 25) ^
|
|
|
|
|
((vpn & mask) >> (shift - VPN_SHIFT)) ;
|
2007-10-11 10:37:10 +00:00
|
|
|
}
|
|
|
|
|
return hash & 0x7fffffffffUL;
|
2007-04-27 01:53:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
extern int __hash_page_4K(unsigned long ea, unsigned long access,
|
|
|
|
|
unsigned long vsid, pte_t *ptep, unsigned long trap,
|
[POWERPC] Provide a way to protect 4k subpages when using 64k pages
Using 64k pages on 64-bit PowerPC systems makes life difficult for
emulators that are trying to emulate an ISA, such as x86, which use a
smaller page size, since the emulator can no longer use the MMU and
the normal system calls for controlling page protections. Of course,
the emulator can emulate the MMU by checking and possibly remapping
the address for each memory access in software, but that is pretty
slow.
This provides a facility for such programs to control the access
permissions on individual 4k sub-pages of 64k pages. The idea is
that the emulator supplies an array of protection masks to apply to a
specified range of virtual addresses. These masks are applied at the
level where hardware PTEs are inserted into the hardware page table
based on the Linux PTEs, so the Linux PTEs are not affected. Note
that this new mechanism does not allow any access that would otherwise
be prohibited; it can only prohibit accesses that would otherwise be
allowed. This new facility is only available on 64-bit PowerPC and
only when the kernel is configured for 64k pages.
The masks are supplied using a new subpage_prot system call, which
takes a starting virtual address and length, and a pointer to an array
of protection masks in memory. The array has a 32-bit word per 64k
page to be protected; each 32-bit word consists of 16 2-bit fields,
for which 0 allows any access (that is otherwise allowed), 1 prevents
write accesses, and 2 or 3 prevent any access.
Implicit in this is that the regions of the address space that are
protected are switched to use 4k hardware pages rather than 64k
hardware pages (on machines with hardware 64k page support). In fact
the whole process is switched to use 4k hardware pages when the
subpage_prot system call is used, but this could be improved in future
to switch only the affected segments.
The subpage protection bits are stored in a 3 level tree akin to the
page table tree. The top level of this tree is stored in a structure
that is appended to the top level of the page table tree, i.e., the
pgd array. Since it will often only be 32-bit addresses (below 4GB)
that are protected, the pointers to the first four bottom level pages
are also stored in this structure (each bottom level page contains the
protection bits for 1GB of address space), so the protection bits for
addresses below 4GB can be accessed with one fewer loads than those
for higher addresses.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-23 21:35:13 +00:00
|
|
|
unsigned int local, int ssize, int subpage_prot);
|
2007-04-27 01:53:52 +00:00
|
|
|
extern int __hash_page_64K(unsigned long ea, unsigned long access,
|
|
|
|
|
unsigned long vsid, pte_t *ptep, unsigned long trap,
|
2007-10-11 10:37:10 +00:00
|
|
|
unsigned int local, int ssize);
|
2007-04-27 01:53:52 +00:00
|
|
|
struct mm_struct;
|
2009-10-26 19:24:31 +00:00
|
|
|
unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
|
2007-04-27 01:53:52 +00:00
|
|
|
extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
|
powerpc/mm: Allow more flexible layouts for hugepage pagetables
Currently each available hugepage size uses a slightly different
pagetable layout: that is, the bottem level table of pointers to
hugepages is a different size, and may branch off from the normal page
tables at a different level. Every hugepage aware path that needs to
walk the pagetables must therefore look up the hugepage size from the
slice info first, and work out the correct way to walk the pagetables
accordingly. Future hardware is likely to add more possible hugepage
sizes, more layout options and more mess.
This patch, therefore reworks the handling of hugepage pagetables to
reduce this complexity. In the new scheme, instead of having to
consult the slice mask, pagetable walking code can check a flag in the
PGD/PUD/PMD entries to see where to branch off to hugepage pagetables,
and the entry also contains the information (eseentially hugepage
shift) necessary to then interpret that table without recourse to the
slice mask. This scheme can be extended neatly to handle multiple
levels of self-describing "special" hugepage pagetables, although for
now we assume only one level exists.
This approach means that only the pagetable allocation path needs to
know how the pagetables should be set out. All other (hugepage)
pagetable walking paths can just interpret the structure as they go.
There already was a flag bit in PGD/PUD/PMD entries for hugepage
directory pointers, but it was only used for debug. We alter that
flag bit to instead be a 0 in the MSB to indicate a hugepage pagetable
pointer (normally it would be 1 since the pointer lies in the linear
mapping). This means that asm pagetable walking can test for (and
punt on) hugepage pointers with the same test that checks for
unpopulated page directory entries (beq becomes bge), since hugepage
pointers will always be positive, and normal pointers always negative.
While we're at it, we get rid of the confusing (and grep defeating)
#defining of hugepte_shift to be the same thing as mmu_huge_psizes.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-10-26 19:24:31 +00:00
|
|
|
int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
|
|
|
|
|
pte_t *ptep, unsigned long trap, int local, int ssize,
|
|
|
|
|
unsigned int shift, unsigned int mmu_psize);
|
2010-07-23 00:31:13 +00:00
|
|
|
extern void hash_failure_debug(unsigned long ea, unsigned long access,
|
|
|
|
|
unsigned long vsid, unsigned long trap,
|
|
|
|
|
int ssize, int psize, unsigned long pte);
|
2007-04-27 01:53:52 +00:00
|
|
|
extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
|
2008-08-05 06:19:56 +00:00
|
|
|
unsigned long pstart, unsigned long prot,
|
2007-10-11 10:37:10 +00:00
|
|
|
int psize, int ssize);
|
2011-06-28 09:54:48 +00:00
|
|
|
extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
|
[POWERPC] Provide a way to protect 4k subpages when using 64k pages
Using 64k pages on 64-bit PowerPC systems makes life difficult for
emulators that are trying to emulate an ISA, such as x86, which use a
smaller page size, since the emulator can no longer use the MMU and
the normal system calls for controlling page protections. Of course,
the emulator can emulate the MMU by checking and possibly remapping
the address for each memory access in software, but that is pretty
slow.
This provides a facility for such programs to control the access
permissions on individual 4k sub-pages of 64k pages. The idea is
that the emulator supplies an array of protection masks to apply to a
specified range of virtual addresses. These masks are applied at the
level where hardware PTEs are inserted into the hardware page table
based on the Linux PTEs, so the Linux PTEs are not affected. Note
that this new mechanism does not allow any access that would otherwise
be prohibited; it can only prohibit accesses that would otherwise be
allowed. This new facility is only available on 64-bit PowerPC and
only when the kernel is configured for 64k pages.
The masks are supplied using a new subpage_prot system call, which
takes a starting virtual address and length, and a pointer to an array
of protection masks in memory. The array has a 32-bit word per 64k
page to be protected; each 32-bit word consists of 16 2-bit fields,
for which 0 allows any access (that is otherwise allowed), 1 prevents
write accesses, and 2 or 3 prevent any access.
Implicit in this is that the regions of the address space that are
protected are switched to use 4k hardware pages rather than 64k
hardware pages (on machines with hardware 64k page support). In fact
the whole process is switched to use 4k hardware pages when the
subpage_prot system call is used, but this could be improved in future
to switch only the affected segments.
The subpage protection bits are stored in a 3 level tree akin to the
page table tree. The top level of this tree is stored in a structure
that is appended to the top level of the page table tree, i.e., the
pgd array. Since it will often only be 32-bit addresses (below 4GB)
that are protected, the pointers to the first four bottom level pages
are also stored in this structure (each bottom level page contains the
protection bits for 1GB of address space), so the protection bits for
addresses below 4GB can be accessed with one fewer loads than those
for higher addresses.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-23 21:35:13 +00:00
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extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
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2007-04-27 01:53:52 +00:00
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extern void hpte_init_native(void);
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extern void hpte_init_lpar(void);
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extern void hpte_init_beat(void);
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2007-10-02 08:23:46 +00:00
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extern void hpte_init_beat_v3(void);
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2007-04-27 01:53:52 +00:00
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extern void stabs_alloc(void);
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extern void slb_initialize(void);
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extern void slb_flush_and_rebolt(void);
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extern void stab_initialize(unsigned long stab);
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2007-08-03 01:55:39 +00:00
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extern void slb_vmalloc_update(void);
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2009-08-28 12:06:29 +00:00
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extern void slb_set_size(u16 size);
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2007-04-27 01:53:52 +00:00
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#endif /* __ASSEMBLY__ */
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/*
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2012-09-10 02:52:56 +00:00
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* VSID allocation (256MB segment)
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2007-04-27 01:53:52 +00:00
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*
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2012-09-10 02:52:56 +00:00
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* We first generate a 38-bit "proto-VSID". For kernel addresses this
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* is equal to the ESID | 1 << 37, for user addresses it is:
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* (context << USER_ESID_BITS) | (esid & ((1U << USER_ESID_BITS) - 1)
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2007-04-27 01:53:52 +00:00
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*
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2012-09-10 02:52:56 +00:00
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* This splits the proto-VSID into the below range
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* 0 - (2^(CONTEXT_BITS + USER_ESID_BITS) - 1) : User proto-VSID range
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* 2^(CONTEXT_BITS + USER_ESID_BITS) - 2^(VSID_BITS) : Kernel proto-VSID range
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*
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* We also have CONTEXT_BITS + USER_ESID_BITS = VSID_BITS - 1
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* That is, we assign half of the space to user processes and half
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* to the kernel.
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2007-04-27 01:53:52 +00:00
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*
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* The proto-VSIDs are then scrambled into real VSIDs with the
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* multiplicative hash:
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*
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* VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
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*
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2012-09-10 02:52:56 +00:00
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* VSID_MULTIPLIER is prime, so in particular it is
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2007-04-27 01:53:52 +00:00
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* co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
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* Because the modulus is 2^n-1 we can compute it efficiently without
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* a divide or extra multiply (see below).
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*
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* This scheme has several advantages over older methods:
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*
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2012-09-10 02:52:56 +00:00
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* - We have VSIDs allocated for every kernel address
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2007-04-27 01:53:52 +00:00
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* (i.e. everything above 0xC000000000000000), except the very top
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* segment, which simplifies several things.
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*
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2012-09-10 02:52:56 +00:00
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* - We allow for USER_ESID_BITS significant bits of ESID and
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* CONTEXT_BITS bits of context for user addresses.
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* i.e. 64T (46 bits) of address space for up to half a million contexts.
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2007-04-27 01:53:52 +00:00
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*
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2012-09-10 02:52:56 +00:00
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* - The scramble function gives robust scattering in the hash
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2007-04-27 01:53:52 +00:00
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* table (at least based on some initial results). The previous
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* method was more susceptible to pathological cases giving excessive
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* hash collisions.
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*/
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2012-09-10 02:52:55 +00:00
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/*
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* This should be computed such that protovosid * vsid_mulitplier
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* doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
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*/
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#define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
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#define VSID_BITS_256M 38
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2007-10-11 10:37:10 +00:00
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#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
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2007-04-27 01:53:52 +00:00
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2007-10-11 10:37:10 +00:00
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#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
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2012-09-10 02:52:55 +00:00
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#define VSID_BITS_1T 26
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2007-10-11 10:37:10 +00:00
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#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
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#define CONTEXT_BITS 19
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2012-09-10 02:52:55 +00:00
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#define USER_ESID_BITS 18
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#define USER_ESID_BITS_1T 6
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2007-04-27 01:53:52 +00:00
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#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
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/*
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* This macro generates asm code to compute the VSID scramble
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* function. Used in slb_allocate() and do_stab_bolted. The function
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* computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
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*
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* rt = register continaing the proto-VSID and into which the
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* VSID will be stored
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* rx = scratch register (clobbered)
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*
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* - rt and rx must be different registers
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2007-10-11 10:37:10 +00:00
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* - The answer will end up in the low VSID_BITS bits of rt. The higher
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2007-04-27 01:53:52 +00:00
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* bits may contain other garbage, so you may need to mask the
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* result.
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*/
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2007-10-11 10:37:10 +00:00
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#define ASM_VSID_SCRAMBLE(rt, rx, size) \
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lis rx,VSID_MULTIPLIER_##size@h; \
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ori rx,rx,VSID_MULTIPLIER_##size@l; \
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2007-04-27 01:53:52 +00:00
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mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
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\
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2007-10-11 10:37:10 +00:00
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srdi rx,rt,VSID_BITS_##size; \
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clrldi rt,rt,(64-VSID_BITS_##size); \
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2007-04-27 01:53:52 +00:00
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add rt,rt,rx; /* add high and low bits */ \
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/* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
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* 2^36-1+2^28-1. That in particular means that if r3 >= \
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* 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
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* the bit clear, r3 already has the answer we want, if it \
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* doesn't, the answer is the low 36 bits of r3+1. So in all \
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* cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
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addi rx,rt,1; \
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2007-10-11 10:37:10 +00:00
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srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
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2007-04-27 01:53:52 +00:00
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add rt,rt,rx
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2012-09-10 02:52:57 +00:00
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/* 4 bits per slice and we have one slice per 1TB */
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#define SLICE_ARRAY_SIZE (PGTABLE_RANGE >> 41)
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2007-04-27 01:53:52 +00:00
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#ifndef __ASSEMBLY__
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2009-11-26 18:56:04 +00:00
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#ifdef CONFIG_PPC_SUBPAGE_PROT
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/*
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* For the sub-page protection option, we extend the PGD with one of
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* these. Basically we have a 3-level tree, with the top level being
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* the protptrs array. To optimize speed and memory consumption when
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* only addresses < 4GB are being protected, pointers to the first
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* four pages of sub-page protection words are stored in the low_prot
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* array.
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* Each page of sub-page protection words protects 1GB (4 bytes
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* protects 64k). For the 3-level tree, each page of pointers then
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* protects 8TB.
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*/
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struct subpage_prot_table {
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unsigned long maxaddr; /* only addresses < this are protected */
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unsigned int **protptrs[2];
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unsigned int *low_prot[4];
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};
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#define SBP_L1_BITS (PAGE_SHIFT - 2)
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#define SBP_L2_BITS (PAGE_SHIFT - 3)
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#define SBP_L1_COUNT (1 << SBP_L1_BITS)
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#define SBP_L2_COUNT (1 << SBP_L2_BITS)
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#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
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#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
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extern void subpage_prot_free(struct mm_struct *mm);
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extern void subpage_prot_init_new_context(struct mm_struct *mm);
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#else
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static inline void subpage_prot_free(struct mm_struct *mm) {}
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static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
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#endif /* CONFIG_PPC_SUBPAGE_PROT */
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2007-04-27 01:53:52 +00:00
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typedef unsigned long mm_context_id_t;
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2011-05-02 20:43:04 +00:00
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struct spinlock;
|
2007-04-27 01:53:52 +00:00
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typedef struct {
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mm_context_id_t id;
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2007-05-08 06:27:27 +00:00
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u16 user_psize; /* page size index */
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#ifdef CONFIG_PPC_MM_SLICES
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u64 low_slices_psize; /* SLB page size encodings */
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2012-09-10 02:52:57 +00:00
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unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
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2007-05-08 06:27:27 +00:00
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#else
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u16 sllp; /* SLB page size encoding */
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2007-04-27 01:53:52 +00:00
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#endif
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unsigned long vdso_base;
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2009-11-26 18:56:04 +00:00
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#ifdef CONFIG_PPC_SUBPAGE_PROT
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struct subpage_prot_table spt;
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#endif /* CONFIG_PPC_SUBPAGE_PROT */
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2011-05-02 20:43:04 +00:00
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#ifdef CONFIG_PPC_ICSWX
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struct spinlock *cop_lockp; /* guard acop and cop_pid */
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unsigned long acop; /* mask of enabled coprocessor types */
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unsigned int cop_pid; /* pid value used with coprocessors */
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#endif /* CONFIG_PPC_ICSWX */
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2007-04-27 01:53:52 +00:00
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} mm_context_t;
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#if 0
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2007-10-11 10:37:10 +00:00
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/*
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* The code below is equivalent to this function for arguments
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* < 2^VSID_BITS, which is all this should ever be called
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* with. However gcc is not clever enough to compute the
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* modulus (2^n-1) without a second multiply.
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*/
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2010-08-02 20:35:18 +00:00
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#define vsid_scramble(protovsid, size) \
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2007-10-11 10:37:10 +00:00
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((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
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2007-04-27 01:53:52 +00:00
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2007-10-11 10:37:10 +00:00
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#else /* 1 */
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#define vsid_scramble(protovsid, size) \
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({ \
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unsigned long x; \
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x = (protovsid) * VSID_MULTIPLIER_##size; \
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x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
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(x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
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})
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2007-04-27 01:53:52 +00:00
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#endif /* 1 */
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2012-09-10 02:52:55 +00:00
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/*
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* This is only valid for addresses >= PAGE_OFFSET
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* The proto-VSID space is divided into two class
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* User: 0 to 2^(CONTEXT_BITS + USER_ESID_BITS) -1
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* kernel: 2^(CONTEXT_BITS + USER_ESID_BITS) to 2^(VSID_BITS) - 1
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*
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* With KERNEL_START at 0xc000000000000000, the proto vsid for
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* the kernel ends up with 0xc00000000 (36 bits). With 64TB
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* support we need to have kernel proto-VSID in the
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* [2^37 to 2^38 - 1] range due to the increased USER_ESID_BITS.
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*/
|
2007-10-11 10:37:10 +00:00
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static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
|
2007-04-27 01:53:52 +00:00
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{
|
2012-09-10 02:52:55 +00:00
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unsigned long proto_vsid;
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/*
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* We need to make sure proto_vsid for the kernel is
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* >= 2^(CONTEXT_BITS + USER_ESID_BITS[_1T])
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*/
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if (ssize == MMU_SEGSIZE_256M) {
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proto_vsid = ea >> SID_SHIFT;
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proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS));
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return vsid_scramble(proto_vsid, 256M);
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}
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proto_vsid = ea >> SID_SHIFT_1T;
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proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T));
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return vsid_scramble(proto_vsid, 1T);
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2007-04-27 01:53:52 +00:00
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}
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2007-10-11 10:37:10 +00:00
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/* Returns the segment size indicator for a user address */
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static inline int user_segment_size(unsigned long addr)
|
2007-04-27 01:53:52 +00:00
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{
|
2007-10-11 10:37:10 +00:00
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/* Use 1T segments if possible for addresses >= 1T */
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if (addr >= (1UL << SID_SHIFT_1T))
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return mmu_highuser_ssize;
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return MMU_SEGSIZE_256M;
|
2007-04-27 01:53:52 +00:00
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}
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|
2007-10-11 10:37:10 +00:00
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/* This is only valid for user addresses (which are below 2^44) */
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static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
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int ssize)
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{
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if (ssize == MMU_SEGSIZE_256M)
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return vsid_scramble((context << USER_ESID_BITS)
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| (ea >> SID_SHIFT), 256M);
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return vsid_scramble((context << USER_ESID_BITS_1T)
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| (ea >> SID_SHIFT_1T), 1T);
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}
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|
2007-04-27 01:53:52 +00:00
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
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