229 lines
11 KiB
PHP
229 lines
11 KiB
PHP
save
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listing off
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;*****************************************************************************
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; REGHC12.INC
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; Register Definitions for HC812A4 & HC912B32
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; Source: MC68HC812A4, MC68HC912B32 Technical Summary (Motorola 1996)
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; 27.01.1997
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; Oliver Thamm (othamm@aol.com)
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;*****************************************************************************
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ifndef reghc12inc ; verhindert Mehrfacheinbindung
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reghc12inc equ 1
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if (MOMCPUNAME<>"68HC12")
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fatal "Falscher Prozessortyp eingestellt: nur 68HC12 erlaubt!"
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endif
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if MOMPASS=1
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message "68HC812A4/68HC912B32-Registerdefinitionen"
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message "(C) 1996,1997 Oliver Thamm"
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endif
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;-----------------------------------------------------------------------------
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REGBASE equ $0000 ; Below: [A=HC812A4|B=HC912B32]
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PORTA equ REGBASE+$0000 ; [A|B] Port A Register
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PORTB equ REGBASE+$0001 ; [A|B] Port B Register
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DDRA equ REGBASE+$0002 ; [A|B] Port A Data Direction Register
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DDRB equ REGBASE+$0003 ; [A|B] Port B Data Direction Register
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PORTC equ REGBASE+$0004 ; [A|-] Port C Register
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PORTD equ REGBASE+$0005 ; [A|-] Port D Register
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DDRC equ REGBASE+$0006 ; [A|-] Port C Data Direction Register
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DDRD equ REGBASE+$0007 ; [A|-] Port D Data Direction Register
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PORTE equ REGBASE+$0008 ; [A|B] Port E Register
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DDRE equ REGBASE+$0009 ; [A|B] Port E Data Direction Register
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PEAR equ REGBASE+$000a ; [A|B] Port E Assignment Register
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MODE equ REGBASE+$000b ; [A|B] Mode Register
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PUCR equ REGBASE+$000c ; [A|B] Pull Up Control Register
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RDRIV equ REGBASE+$000d ; [A|B] Reduced Drive of I/O Lines
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INITRM equ REGBASE+$0010 ; [A|B] Initialization of Internal RAM Position Register
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INITRG equ REGBASE+$0011 ; [A|B] Initialization of Internal Register Position Register
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INITEE equ REGBASE+$0012 ; [A|B] Initialization of Internal EEPROM Position Register
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MISC equ REGBASE+$0013 ; [A|B] Miscellaneous Mapping Register
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RTICTL equ REGBASE+$0014 ; [A|B] Real-Time Interrupt Control Register
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RTIFLG equ REGBASE+$0015 ; [A|B] Real-Time Interrupt Flag Register
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COPCTL equ REGBASE+$0016 ; [A|B] COP Control Register
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COPRST equ REGBASE+$0017 ; [A|B] Arm/Reset COP Timer Register
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ITST0 equ REGBASE+$0018 ; [A|B] Reserved
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ITST1 equ REGBASE+$0019 ; [A|B] Reserved
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ITST2 equ REGBASE+$001a ; [A|B] Reserved
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ITST3 equ REGBASE+$001b ; [A|B] Reserved
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INTCR equ REGBASE+$001e ; [A|B] Interrupt Control Register
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HPRIO equ REGBASE+$001f ; [A|B] Highest Priority I Interrupt
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KWIED equ REGBASE+$0020 ; [A|-] Key Wakeup Port D Interrupt Enable Register
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BRKCT0 equ REGBASE+$0020 ; [-|B] Breakpoint Control Register 0
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KWIFD equ REGBASE+$0021 ; [A|-] Key Wakeup Port D Flag Register
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BRKCT1 equ REGBASE+$0021 ; [-|B] Breakpoint Control Register 1
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BRKAH equ REGBASE+$0022 ; [-|B] Breakpoint Address Register (High Byte)
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BRKAL equ REGBASE+$0023 ; [-|B] Breakpoint Address Register (Low Byte)
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PORTH equ REGBASE+$0024 ; [A|-] Port H Register
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BRKDH equ REGBASE+$0024 ; [-|B] Breakpoint Data Register (High Byte)
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DDRH equ REGBASE+$0025 ; [A|-] Port H Data Direction Register
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BRKDL equ REGBASE+$0025 ; [-|B] Breakpoint Data Register (Low Byte)
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KWIEH equ REGBASE+$0026 ; [A|-] Key Wakeup Port H Interrupt Enable Register
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KWIFH equ REGBASE+$0027 ; [A|-] Key Wakeup Port H Flag Register
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PORTJ equ REGBASE+$0028 ; [A|-] Port J Register
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DDRJ equ REGBASE+$0029 ; [A|-] Port J Data Direction Register
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KWIEJ equ REGBASE+$002a ; [A|-] Key Wakeup Port J Interrupt Enable Register
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KWIFJ equ REGBASE+$002b ; [A|-] Key Wakeup Port J Flag Register
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KPOLJ equ REGBASE+$002c ; [A|-] Key Wakeup Port J Polarity Register
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PUPSJ equ REGBASE+$002d ; [A|-] Key Wakeup Port J Pull-Up/Pulldown Select Register
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PULEJ equ REGBASE+$002e ; [A|-] Key Wakeup Port J Pull-Up/Pulldown Enable Register
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PORTF equ REGBASE+$0030 ; [A|-] Port F Register
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PORTG equ REGBASE+$0031 ; [A|-] Port G Register
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DDRF equ REGBASE+$0032 ; [A|-] Port F Data Direction Register
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DDRG equ REGBASE+$0033 ; [A|-] Port G Data Direction Register
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DPAGE equ REGBASE+$0034 ; [A|-] Data Page Register
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PPAGE equ REGBASE+$0035 ; [A|-] Program Page Register
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EPAGE equ REGBASE+$0036 ; [A|-] Extra Page Register
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WINDEF equ REGBASE+$0037 ; [A|-] Window Definition Register
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MXAR equ REGBASE+$0038 ; [A|-] Memory Expansion Assignment Register
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CSCTL0 equ REGBASE+$003c ; [A|-] Chip Select Control Register 0
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CSCTL1 equ REGBASE+$003d ; [A|-] Chip Select Control Register 1
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CSSTR0 equ REGBASE+$003e ; [A|-] Chip Select Stretch Register 0
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CSSTR1 equ REGBASE+$003f ; [A|-] Chip Select Stretch Register 1
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LDV equ REGBASE+$0040 ; [A|-] Loop Divider Registers (Word)
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PWCLK equ REGBASE+$0040 ; [-|B] PWM Clocks and Concatenate
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PWPOL equ REGBASE+$0041 ; [-|B] PWM Clock Select and Polarity
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RDV equ REGBASE+$0042 ; [A|-] Reference Divider Register (Word)
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PWEN equ REGBASE+$0042 ; [-|B] PWM Enable
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PWPRES equ REGBASE+$0043 ; [-|B] PWM Prescale Counter
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PWSCAL0 equ REGBASE+$0044 ; [-|B] PWM Scale Register 0
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PWSCNT0 equ REGBASE+$0045 ; [-|B] PWM Scale Counter 0 Value
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PWSCAL1 equ REGBASE+$0046 ; [-|B] PWM Scale Register 1
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CLKCTL equ REGBASE+$0047 ; [A|-] Clock Control Register
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PWSCNT1 equ REGBASE+$0047 ; [-|B] PWM Scale Counter 1 Value
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PWCNT0 equ REGBASE+$0048 ; [-|B] PWM Channel 0 Counter
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PWCNT1 equ REGBASE+$0049 ; [-|B] PWM Channel 1 Counter
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PWCNT2 equ REGBASE+$004a ; [-|B] PWM Channel 2 Counter
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PWCNT3 equ REGBASE+$004b ; [-|B] PWM Channel 3 Counter
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PWPER0 equ REGBASE+$004c ; [-|B] PWM Channel 0 Period Register
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PWPER1 equ REGBASE+$004d ; [-|B] PWM Channel 1 Period Register
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PWPER2 equ REGBASE+$004e ; [-|B] PWM Channel 2 Period Register
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PWPER3 equ REGBASE+$004f ; [-|B] PWM Channel 3 Period Register
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PWDTY0 equ REGBASE+$0050 ; [-|B] PWM Channel 0 Duty Register
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PWDTY1 equ REGBASE+$0051 ; [-|B] PWM Channel 1 Duty Register
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PWDTY2 equ REGBASE+$0052 ; [-|B] PWM Channel 2 Duty Register
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PWDTY3 equ REGBASE+$0053 ; [-|B] PWM Channel 3 Duty Register
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PWCTL equ REGBASE+$0054 ; [-|B] PWM Control Register
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PWTST equ REGBASE+$0055 ; [-|B] PWM Special Mode Register
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PORTP equ REGBASE+$0056 ; [-|B] Port P Data Register
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DDRP equ REGBASE+$0057 ; [-|B] Port P Data Direction Register
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ATDCTL0 equ REGBASE+$0060 ; [A|B] Reserved
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ATDCTL1 equ REGBASE+$0061 ; [A|B] Reserved
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ATDCTL2 equ REGBASE+$0062 ; [A|B] ATD Control Register 2
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ATDCTL3 equ REGBASE+$0063 ; [A|B] ATD Control Register 3
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ATDCTL4 equ REGBASE+$0064 ; [A|B] ATD Control Register 4
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ATDCTL5 equ REGBASE+$0065 ; [A|B] ATD Control Register 5
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ATDSTAT equ REGBASE+$0066 ; [A|B] ATD Status Register (Word)
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ATDTEST equ REGBASE+$0068 ; [A|B] ATD Test Register (Word)
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PORTAD equ REGBASE+$006f ; [A|B] Port AD Data Input Register
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ADR0H equ REGBASE+$0070 ; [A|B] A/D Converter Result Register 0
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ADR1H equ REGBASE+$0072 ; [A|B] A/D Converter Result Register 1
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ADR2H equ REGBASE+$0074 ; [A|B] A/D Converter Result Register 2
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ADR3H equ REGBASE+$0076 ; [A|B] A/D Converter Result Register 3
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ADR4H equ REGBASE+$0078 ; [A|B] A/D Converter Result Register 4
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ADR5H equ REGBASE+$007a ; [A|B] A/D Converter Result Register 5
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ADR6H equ REGBASE+$007c ; [A|B] A/D Converter Result Register 6
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ADR7H equ REGBASE+$007e ; [A|B] A/D Converter Result Register 7
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TIOS equ REGBASE+$0080 ; [A|B] Timer Input Capture/Output Compare Select
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CFORC equ REGBASE+$0081 ; [A|B] Timer Compare Force Register
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OC7M equ REGBASE+$0082 ; [A|B] Output Compare 7 Mask Register
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OC7D equ REGBASE+$0083 ; [A|B] Output Compare 7 Data Register
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TCNT equ REGBASE+$0084 ; [A|B] Timer Count Register (Word)
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TSCR equ REGBASE+$0086 ; [A|B] Timer System Control Register
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TQCR equ REGBASE+$0087 ; [A|B] Reserved
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TCTL1 equ REGBASE+$0088 ; [A|B] Timer Control Register 1
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TCTL2 equ REGBASE+$0089 ; [A|B] Timer Control Register 2
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TCTL3 equ REGBASE+$008a ; [A|B] Timer Control Register 3
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TCTL4 equ REGBASE+$008b ; [A|B] Timer Control Register 4
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TMSK1 equ REGBASE+$008c ; [A|B] Timer Interrupt Mask 1
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TMSK2 equ REGBASE+$008d ; [A|B] Timer Interrupt Mask 2
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TFLG1 equ REGBASE+$008e ; [A|B] Timer Interrupt Flag 1
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TFLG2 equ REGBASE+$008f ; [A|B] Timer Interrupt Flag 2
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TC0 equ REGBASE+$0090 ; [A|B] Timer Input Capture/Output Compare Register 0 (Word)
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TC1 equ REGBASE+$0092 ; [A|B] Timer Input Capture/Output Compare Register 1 (Word)
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TC2 equ REGBASE+$0094 ; [A|B] Timer Input Capture/Output Compare Register 2 (Word)
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TC3 equ REGBASE+$0096 ; [A|B] Timer Input Capture/Output Compare Register 3 (Word)
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TC4 equ REGBASE+$0098 ; [A|B] Timer Input Capture/Output Compare Register 4 (Word)
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TC5 equ REGBASE+$009a ; [A|B] Timer Input Capture/Output Compare Register 5 (Word)
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TC6 equ REGBASE+$009c ; [A|B] Timer Input Capture/Output Compare Register 6 (Word)
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TC7 equ REGBASE+$009e ; [A|B] Timer Input Capture/Output Compare Register 7 (Word)
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PACTL equ REGBASE+$00a0 ; [A|B] Pulse Accumulator Control Register
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PAFLG equ REGBASE+$00a1 ; [A|B] Pulse Accumulator Flag Register
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PACNT equ REGBASE+$00a2 ; [A|B] 16-bit Pulse Accumulator Count Register (Word)
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TIMTST equ REGBASE+$00ad ; [A|B] Timer Test Register
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PORTT equ REGBASE+$00ae ; [A|B] Port T Register
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DDRT equ REGBASE+$00af ; [A|B] Port T Data Direction Register
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SC0BDH equ REGBASE+$00c0 ; [A|B] SCI 0 Baud Rate Control Register High
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SC0BDL equ REGBASE+$00c1 ; [A|B] SCI 0 Baud Rate Control Register Low
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SC0CR1 equ REGBASE+$00c2 ; [A|B] SCI 0 Control Register 1
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SC0CR2 equ REGBASE+$00c3 ; [A|B] SCI 0 Control Register 2
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SC0SR1 equ REGBASE+$00c4 ; [A|B] SCI 0 Status Register 1
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SC0SR2 equ REGBASE+$00c5 ; [A|B] SCI 0 Status Register 2
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SC0DRH equ REGBASE+$00c6 ; [A|B] SCI 0 Data Register High
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SC0DRL equ REGBASE+$00c7 ; [A|B] SCI 0 Data Register Low
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SC1BDH equ REGBASE+$00c8 ; [A|-] SCI 1 Baud Rate Control Register High
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SC1BDL equ REGBASE+$00c9 ; [A|-] SCI 1 Baud Rate Control Register Low
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SC1CR1 equ REGBASE+$00ca ; [A|-] SCI 1 Control Register 1
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SC1CR2 equ REGBASE+$00cb ; [A|-] SCI 1 Control Register 2
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SC1SR1 equ REGBASE+$00cc ; [A|-] SCI 1 Status Register 1
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SC1SR2 equ REGBASE+$00cd ; [A|-] SCI 1 Status Register 2
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SC1DRH equ REGBASE+$00ce ; [A|-] SCI 1 Data Register High
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SC1DRL equ REGBASE+$00cf ; [A|-] SCI 1 Data Register Low
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SP0CR1 equ REGBASE+$00d0 ; [A|B] SPI Control Register 1
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SP0CR2 equ REGBASE+$00d1 ; [A|B] SPI Control Register 2
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SP0BR equ REGBASE+$00d2 ; [A|B] SPI Baud Rate Register
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SP0SR equ REGBASE+$00d3 ; [A|B] SPI Status Register
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SP0DR equ REGBASE+$00d5 ; [A|B] SPI Data Register
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PORTS equ REGBASE+$00d6 ; [A|B] Port S Register
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DDRS equ REGBASE+$00d7 ; [A|B] Port S Data Direction Register
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PURDS equ REGBASE+$00db ; [-|B] Pullup and Reduced Drive for Port S
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EEMCR equ REGBASE+$00f0 ; [A|B] EEPROM Module Configuration
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EEPROT equ REGBASE+$00f1 ; [A|B] EEPROM Block Protect
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EETST equ REGBASE+$00f2 ; [A|B] EEPROM Test
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EEPROG equ REGBASE+$00f3 ; [A|B] EEPROM Control
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FEELCK equ REGBASE+$00f4 ; [-|B] Flash EEPROM Lock Control Register
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FEEMCR equ REGBASE+$00f5 ; [-|B] Flash EEPROM Module Configuration Register
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FEETST equ REGBASE+$00f6 ; [-|B] Flash EEPROM Module Test Register
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FEECTL equ REGBASE+$00f7 ; [-|B] Flash EEPROM Control Register
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BCR1 equ REGBASE+$00f8 ; [-|B] BDLC Control Register 1
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BSVR equ REGBASE+$00f9 ; [-|B] BDLC State Vector Register
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BCR2 equ REGBASE+$00fa ; [-|B] BDLC Control Register 2
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BDR equ REGBASE+$00fb ; [-|B] BDLC Data Register
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BARD equ REGBASE+$00fc ; [-|B] BDLC Analog Roundtrip Delay Register
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DLCSCR equ REGBASE+$00fd ; [-|B] Port DLC Control Register
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PORTDLC equ REGBASE+$00fe ; [-|B] Port DLC Data Register
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DDRDLC equ REGBASE+$00ff ; [-|B] Port DLC Data Direction Register
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;-----------------------------------------------------------------------------
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endif ; von IFDEF...
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restore ; wieder erlauben
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