561 lines
20 KiB
PHP
561 lines
20 KiB
PHP
save
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listing off
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; kein Listing über diesen File
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;****************************************************************************
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;* *
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;* AS 1.41 - Datei REG3048.INC *
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;* *
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;* Sinn : enthält SFR-, Makro- und Adreadefinitionen für H8/3048 *
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;* *
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;* letzte Änderungen : 24.10.1995 *
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;* *
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;****************************************************************************
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ifndef reg3048inc ; verhindert Mehrfacheinbindung
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reg532inc equ 1
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if (MOMCPUNAME<>"HD6413309")&&(MOMCPUNAME<>"H8/300H")
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fatal "Falscher Prozessortyp eingestellt: nur H8/300H erlaubt!"
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endif
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if MOMPASS=1
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message "H8/3048-SFR-Definitionen, (C) 1995 Christian Stelter"
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endif
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;-----------------------------------------------------------------------------
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; MCU-Operating-Modes: (Sec.3 p.55-68 & Sec.20 p.615-628)
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MDCR equ $fff1 ; Arbeitsmodus CPU
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SYSCR equ $fff2 ; Standby-Modusregister
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MSTCR equ $ff5e ; Module standby control register
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;MDCR-Register
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MD0 equ 0
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MD1 equ 1
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MD2 equ 2
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;SYSCR-Register
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SSBY equ 7 ; Software-Standby
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STS2 equ 6 ; Standby-Timer Select
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STS1 equ 5
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STS0 equ 4
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UE equ 3 ; User bit enable
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NMIEG equ 2 ; NMI-edge
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RAME equ 0 ; internes RAM freigeben
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;MSTCR-Register
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PSTOP equ 7 ; Phi-clock stop
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MSTOP5 equ 5 ; Module standby
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MSTOP4 equ 4
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MSTOP3 equ 3
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MSTOP2 equ 2
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MSTOP1 equ 1
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MSTOP0 equ 0
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;-----------------------------------------------------------------------------
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; Bus-Controller (Sec.6 p.107-142)
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ABWCR equ $ffec ; Bus width control register
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ASTCR equ $ffed ; Access state control register
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WCR equ $ffee ; Wait control register
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WMS0 equ 2 ; Modus
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WMS1 equ 3
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WC0 equ 0 ; Anzahl Waitstates
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WC1 equ 1
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WCER equ $ffef ; Wait state controller enable reg.
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BRCR equ $fff3 ; Bus release control register
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A23E equ 7 ; Address 23 enable
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A22E equ 6 ; 22
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A21E equ 5 ; 21
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BRLE equ 0 ; Bus release enable
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CSCR equ $ff5f ; Chip select control register
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CS7E equ 7 ; Chip-select 7 enabel
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CS6E equ 6
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CS5E equ 5
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CS4E equ 4
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;-----------------------------------------------------------------------------
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; Interrupt-Controller:
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ISCR equ $fff4 ; IRQ sense control register
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IER equ $fff5 ; IRQ enable register
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ISR equ $fff6 ; IRQ status register
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IPRA equ $fff8 ; Prioritätssteuerung
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IPRB equ $fff9 ;
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;-----------------------------------------------------------------------------
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; Lage Exception und Interrupt-Vektoren: (Sec.4 p.69-78)
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;
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__defvec macro Name,Num
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Name equ Num<<2
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endm
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__defvec Reset,0
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__defvec NMI,7
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__defvec TRAP0,8
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__defvec TRAP1,9
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__defvec TRAP2,10
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__defvec TRAP3,11
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__defvec IRQ0,12
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__defvec IRQ1,13
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__defvec IRQ2,14
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__defvec IRQ3,15
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__defvec IRQ4,16
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__defvec IRQ5,17
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__defvec WOVI,20
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__defvec CMI,21
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__defvec IMIA0,24
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__defvec IMIB0,25
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__defvec OVI0,26
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__defvec IMIA1,28
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__defvec IMIB1,29
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__defvec OVI1,30
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__defvec IMIA2,32
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__defvec IMIB2,33
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__defvec OVI2,34
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__defvec IMIA3,36
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__defvec IMIB3,37
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__defvec OVI3,38
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__defvec IMIA4,40
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__defvec IMIB4,41
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__defvec OVI4,42
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__defvec DEND0A,44
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;__defvec DEND0A,45
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__defvec DEND1B,46
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;__defvec DEND1B,47
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__defvec ERI0,52
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__defvec RXI0,53
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__defvec TXI0,54
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__defvec TEI0,55
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__defvec ERI1,56
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__defvec RXI1,57
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__defvec TXI1,58
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__defvec TEI1,59
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__defvec ADI,60
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;-----------------------------------------------------------------------------
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; DMA-Controller (Sec.6 p.181-238)
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DTEA equ $fff4 ; Freigabe Datentransfers
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DTEB equ $fff5
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DTEC equ $fff6
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DTED equ $fff7
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__defdma macro Base,Name
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MAR{Name}AR equ Base ; Memory address register AR
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MAR{Name}ER equ Base+1 ; Memory address register AE
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MAR{Name}AL equ Base+2 ; Memory address register AL
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MAR{Name}AH equ Base+3 ; Memory address register AH
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ETCR{Name}AH equ Base+4 ; Execute transfer count register AH
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ETCR{Name}AL equ Base+5 ; AL
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IOAR{Name}A equ Base+6 ; I/O address register A
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DTCR{Name}A equ Base+7 ; Data transfer control register A
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MAR{Name}BR equ Base+8 ; Memory address register BR
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MAR{Name}BE equ Base+9 ; Memory address register BE
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MAR{Name}BH equ Base+10 ; Memory address register BH
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MAR{Name}BL equ Base+11 ; Memory address register BL
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ETCR{Name}BH equ Base+12 ; Excute transfer count register BH
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ETCR{Name}BL equ Base+13 ; Excute transfer count register BL
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IOAR{Name}B equ Base+14 ; I/O address register B
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DTCR{Name}B equ Base+15 ; Data transfer control register
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endm
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__defdma $ff20,"0"
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__defdma $ff30,"1"
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; DTCR-Register
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; short address-mode
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DTE equ 7 ; Data transfer enable
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DTSZ equ 6 ; Data transfer size
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DTID equ 5 ; Data transfer inc/dec
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RPE equ 4 ; Repeat enable
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DTIE equ 3 ; Data transfer interrupt enable
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DTS2 equ 2 ; Data transfer select
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DTS1 equ 1
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DTS0 equ 0
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; full address mode
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SAID equ 5 ; Source address inc/dec
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SAIE equ 4 ; Source address inc/dec enable
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DTS2A equ 2 ; Data transfer select
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DTS1A equ 1
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DTS0A equ 0
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; DTCRB-Register
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DTME equ 7 ; Data transfer master enable
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DAID equ 5 ; Destination address inc/dec bit
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DAIE equ 4 ; enable
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TMS equ 3 ; Transfer mode select
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DTS2B equ 2 ; Data transfer select
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DTS1B equ 1
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DTS0B equ 0
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;-----------------------------------------------------------------------------
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; I/O-Ports: (Sec.9 p.239-280)
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P1DDR equ $ffc0 ; Datenrichtung Port 1
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P1DR equ $ffc2 ; Daten Port 1
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P2DDR equ $ffc1 ; Datenrichtung Port 2
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P2DR equ $ffc3 ; Daten Port 2
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P2PCR equ $ffd8 ; Input pull-up control register port 3
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P3DDR equ $ffc4 ; Datenrichtung Port 3
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P3DR equ $ffc6 ; Daten Port 3
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P4DDR equ $ffc5 ; Datenrichtung Port 4
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P4DR equ $ffc7 ; Daten Port 4
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P4PCR equ $ffda ; Input pull-up control register port 4
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P5DDR equ $ffc8 ; Datenrichtung Port 5
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P5DR equ $ffca ; Daten Port 5
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P5PCR equ $ffcb ; Input pull-up control register port 5
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P6DDR equ $ffc9 ; Datenrichtung Port 6
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P6DR equ $ffcb ; Daten Port 6
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P8DDR equ $ffcd ; Datenrichtung Port 8
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P8DR equ $ffcf ; Daten Port 8
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P9DDR equ $ffd0 ; Datenrichtung Port 9
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P9DR equ $ffd2 ; Daten Port 9
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PADDR equ $ffd1 ; Datenrichtung Port A
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PADR equ $ffd3 ; Daten Port A
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PBDDR equ $ffd4 ; Datenrichtung Port B
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PBDR equ $ffd6 ; Daten Port B
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;------------------------------------------------------------------------------
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;Integrated Timer Unit (ITU): (Sec.10 p.281-380)
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;common
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TSTR equ $ff60 ; Timer start register
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TSNC equ $ff61 ; Timer synchro register
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TMDR equ $ff62 ; Timer mode register
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TFCR equ $ff63 ; Timer function control register
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TOER equ $ff90 ; Timer output master enable register
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TOCR equ $ff91 ; Timer output control register
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__deftimer macro Base,Name
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TCR{Name} equ Base ; Timer control register
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TIOR{Name} equ Base+1 ; Timer I/O control register
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TIER{Name} equ Base+2 ; Timer interrupt enable register
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TSR{Name} equ Base+3 ; Timer status register
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TCNT{Name}H equ Base+4 ; Timer counter H
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TCNT{Name}L equ Base+5 ; Timer counter L
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GRA{Name}H equ Base+6 ; General register A (high)
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GRA{Name}L equ Base+7 ; General register A (low)
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GRB{Name}H equ Base+8 ; General register B (high)
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GRB{Name}L equ Base+9 ; General register B (low)
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endm
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__deftimer $ff64,"0"
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__deftimer $ff6e,"1"
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__deftimer $ff78,"2"
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__deftimer $ff82,"3"
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BRA3H equ $ff8c ; Buffer register A3 (high)
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BRA3L equ $ff8d ; Buffer register A3 (low)
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BRB3H equ $ff8e ; Buffer register B3 (high)
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BRB3L equ $ff8f ; Buffer register B3 (low)
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__deftimer $ff82,"4"
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BRA4H equ $ff9c ; Buffer register A4 (high)
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BRA4L equ $ff9d ; Buffer register A4 (low)
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BRB4H equ $ff9e ; Buffer register B4 (high)
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BRB4L equ $ff9f ; Buffer register B4 (low)
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;TMDR-Register
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MDF equ 6 ; Phase counting mode flag
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FDIR equ 5 ; Flag direction
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PWM4 equ 4 ; PWM mode
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PWM3 equ 3
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PWM2 equ 2
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PWM1 equ 1
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PWM0 equ 0
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;TFCR-Register
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CMD1 equ 5 ; Combination mode
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CMD0 equ 4
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BFB4 equ 3 ; Buffer mode B4
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BFA4 equ 2 ; Buffer mode A4
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BFB3 equ 1 ; Buffer mode B3
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BFA3 equ 0 ; Buffer mode A3
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;TOER-Register
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EXB4 equ 5 ; Master enable TOCXB4
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EXA4 equ 4 ; Master enable TOCXA4
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EB3 equ 3 ; Master enable TIOCB3
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EB4 equ 2 ; Master enable TIOCB4
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EA4 equ 1 ; Master enable TIOCA4
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EA3 equ 0 ; Master enable TIOCA3
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;TOCR-Register
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XTGD equ 4 ; External trigger disable
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OLS4 equ 1 ; Output level select 4
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OLS3 equ 0 ; Output level select 3
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;TCR-Register
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CCLR1 equ 6 ; Counter clear
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CCLR0 equ 5
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CKEG1 equ 4 ; Counter edge
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CKEG0 equ 3
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TPSC2 equ 2 ; Timer prescaler
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TPSC1 equ 1
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TPSC0 equ 0
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;TIOR-Register
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IOB2 equ 6 ; I/O control B2
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IOB1 equ 5 ; I/O control B1
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IOB0 equ 4 ; I/O control B0
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IOA2 equ 2 ; I/O control A2
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IOA1 equ 1 ; I/O control A1
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IOA0 equ 0 ; I/O control A0
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;TSR-Register
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OVF equ 2 ; Overflow flag
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IMFB equ 1 ; Input capture / compare match flag B
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IMFA equ 0 ; Input capture / compare match flag A
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;TIER-Register
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OVIE equ 2 ; Overflow interrupt enable
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IMIEB equ 1 ; Input capture / compare match interrupt enable B
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IMIEA equ 0 ; Input capture / compare match interrupt enable A
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;-----------------------------------------------------------------------------
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;Programmable Timing Pattern Controller (Sec.11 p.381-406)
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TPMR equ $ffa0 ; TPC output mode register
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TPCR equ $ffa1 ; TPC output control register
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NDERB equ $ffa2 ; Next data enable register B
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NDERA equ $ffa3 ; Next data enable register A
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NDRA equ $ffa5 ; Next data register A
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NDRB equ $ffa4 ; Next data register B
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NDRA1 equ $ffa5 ; Next data register A group 1
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NDRA0 equ $ffa7 ; Next data register A group 0
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NDRB3 equ $ffa4 ; Next data register B group 3
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NDRB2 equ $ffa6 ; Next data register B group 2
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;-----------------------------------------------------------------------------
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; Watchdog: (Sec.12 p.407-422)
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WDT_TCSR equ $ffa8 ; Timer control/status register
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WDT_TCNT equ $ffa9 ; Timer counter
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WDT_RSTCSR equ $ffab ; Reset control/status register
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WDT_RSTCSRW equ $ffaa ; dito, zum setzen wordzugriffe (p.415)
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;TCSR-Register
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WDT_OVF equ 7 ; Overflow Flag
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WDT_WTIT equ 6 ; Timer mode select
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WDT_TME equ 5 ; Timer enable
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WDT_CKS2 equ 2 ; Clock select
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WDT_CKS1 equ 1
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WDT_CKS0 equ 0
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;RSTCSR-Register
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WDT_WRST equ 7 ; Watchdog timer reset
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WDT_RSTOE equ 6 ; Reset output enable
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;-----------------------------------------------------------------------------
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; serielle Schnittstelle: (Sec.13 p.423-482)
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__defSCI macro Base,Name
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SMR{Name} equ Base ; Serial mode register
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BRR{Name} equ Base+1 ; Bit rate register
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SCR{Name} equ Base+2 ; Serial control register
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TDR{Name} equ Base+3 ; Transmit data register
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SSR{Name} equ Base+4 ; Serial status register
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RDR{Name} equ Base+5 ; Receive data register
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endm
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__defSCI $ffb0,"0"
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__defSCI $ffb8,"1"
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;SMR-Register
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CA equ 7 ; Communication mode
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CHR equ 6 ; Character length
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PE equ 5 ; Parity enable
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OE equ 4 ; Parity mode
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STOP equ 3 ; Stop bit length
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MP equ 2 ; Multiprocessor mode
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CKS1 equ 1 ; Clock select 1
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CKS0 equ 0
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;SCR-Register
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TIE equ 7 ; Transmit interrupt enable
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RIE equ 6 ; Receive " "
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TE equ 5 ; Transmit enable
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RE equ 4 ; Receive enable
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MPIE equ 3 ; Multiprozessor interrupt enable
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TEIE equ 2 ; Transmit-end interrupt enable
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CKE1 equ 1 ; Clock enable 1
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CKE0 equ 0 ;
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;SSR-Register
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TDRE equ 7 ; Transmit data register empty
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RDRF equ 6 ; Receive data register full
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ORER equ 5 ; Overrun error
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FER equ 4 ; Framing error
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PER equ 3 ; Parity error
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TEND equ 2 ; Transmit end
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MPB equ 1 ; Multiprocessor bit
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MPBT equ 0 ; Multiprocessor bit transfer
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;-----------------------------------------------------------------------------
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;Smart Card interface
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;not implemented yet
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;-----------------------------------------------------------------------------
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; A/D-Wandler: (Sec.15 p.505-526)
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ADDRA equ $ffe0
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ADDRAH equ $ffe0 ;
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ADDRAL equ $ffe1 ;
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ADDRB equ $ffe2
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ADDRBH equ $ffe2
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ADDRBL equ $ffe3
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ADDRC equ $ffe4
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ADDRCH equ $ffe4
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ADDRCL equ $ffe5
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ADDRD equ $ffe6
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ADDRDH equ $ffe6
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ADDRDL equ $ffe7
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ADCSR equ $ffe8 ; Steuer/Statusregister:
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ADF equ 7 ; Wandlung abgeschlossen
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ADIE equ 6 ; Interrupt bei Wandelende?
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ADST equ 5 ; Wandlung starten
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SCAN equ 4 ; Scan-Modus
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CKS equ 3 ; Wandlungszeit
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CH2 equ 2 ; Kanalauswahl
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CH1 equ 1
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CH0 equ 0
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ADCR equ $ffe9 ; A/D control register
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TRGE equ 7 ; Trigger enable
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;-----------------------------------------------------------------------------
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;D/A-Wandler (Sec.16 p.527-533)
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DADR0 equ $ffdc ; D/A data register 0
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DADR1 equ $ffdd ; D/A data register 1
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DACR equ $ffde ; D/A control register
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DASTCR equ $ff5c ; D/A standby control register
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;DACR-Register
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DAOE1 equ 7 ; D/A output enable
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DAOE0 equ 6
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DAE equ 5 ; D/A enable
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;DASTCR-Register
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DASTE equ 0 ; D/A standby enable
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;-----------------------------------------------------------------------------
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;Clock-Pulse Generator (Sec.19 p.607-614)
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DIVCR equ $ff5d ; Divison control register
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DIV1 equ 1
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DIV0 equ 0
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;-----------------------------------------------------------------------------
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;-----------------------------------------------------------------------------
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endif
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restore
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